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@@ -1,6 +1,6 @@
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-- nios2_uc.vhd
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+-- Generated using ACDS version 18.1 625
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library IEEE;
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use IEEE.std_logic_1164.all;
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@@ -8,9 +8,15 @@ use IEEE.numeric_std.all;
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entity nios2_uc is
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port (
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- clk_clk : in std_logic := '0'; -- clk.clk
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- pio_led_ext_conn_export : out std_logic_vector(31 downto 0); -- pio_led_ext_conn.export
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- reset_reset_n : in std_logic := '0' -- reset.reset_n
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+ clk_clk : in std_logic := '0'; -- clk.clk
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+ lcd_16207_ext_RS : out std_logic; -- lcd_16207_ext.RS
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+ lcd_16207_ext_RW : out std_logic; -- .RW
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+ lcd_16207_ext_data : inout std_logic_vector(7 downto 0) := (others => '0'); -- .data
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+ lcd_16207_ext_E : out std_logic; -- .E
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+ pio_button_ext_conn_export : in std_logic_vector(7 downto 0) := (others => '0'); -- pio_button_ext_conn.export
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+ pio_led_ext_conn_export : out std_logic_vector(31 downto 0); -- pio_led_ext_conn.export
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+ pio_matrix_ext_conn_export : out std_logic_vector(19 downto 0); -- pio_matrix_ext_conn.export
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+ reset_reset_n : in std_logic := '0' -- reset.reset_n
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);
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end entity nios2_uc;
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@@ -30,6 +36,23 @@ architecture rtl of nios2_uc is
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);
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end component nios2_uc_jtag_uart;
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+ component nios2_uc_lcd_16207 is
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+ port (
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+ reset_n : in std_logic := 'X'; -- reset_n
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+ clk : in std_logic := 'X'; -- clk
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+ begintransfer : in std_logic := 'X'; -- begintransfer
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+ read : in std_logic := 'X'; -- read
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+ write : in std_logic := 'X'; -- write
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+ readdata : out std_logic_vector(7 downto 0); -- readdata
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+ writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
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+ address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
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+ LCD_RS : out std_logic; -- export
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+ LCD_RW : out std_logic; -- export
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+ LCD_data : inout std_logic_vector(7 downto 0) := (others => 'X'); -- export
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+ LCD_E : out std_logic -- export
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+ );
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+ end component nios2_uc_lcd_16207;
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+
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component nios2_uc_nios2 is
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port (
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clk : in std_logic := 'X'; -- clk
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@@ -57,10 +80,44 @@ architecture rtl of nios2_uc is
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debug_mem_slave_waitrequest : out std_logic; -- waitrequest
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debug_mem_slave_write : in std_logic := 'X'; -- write
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debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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- dummy_ci_port : out std_logic -- readra
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+ E_ci_multi_done : in std_logic := 'X'; -- done
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+ E_ci_multi_clk_en : out std_logic; -- clk_en
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+ E_ci_multi_start : out std_logic; -- start
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+ E_ci_result : in std_logic_vector(31 downto 0) := (others => 'X'); -- result
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+ D_ci_a : out std_logic_vector(4 downto 0); -- a
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+ D_ci_b : out std_logic_vector(4 downto 0); -- b
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+ D_ci_c : out std_logic_vector(4 downto 0); -- c
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+ D_ci_n : out std_logic_vector(7 downto 0); -- n
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+ D_ci_readra : out std_logic; -- readra
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+ D_ci_readrb : out std_logic; -- readrb
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+ D_ci_writerc : out std_logic; -- writerc
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+ E_ci_dataa : out std_logic_vector(31 downto 0); -- dataa
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+ E_ci_datab : out std_logic_vector(31 downto 0); -- datab
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+ E_ci_multi_clock : out std_logic; -- clk
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+ E_ci_multi_reset : out std_logic; -- reset
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+ E_ci_multi_reset_req : out std_logic; -- reset_req
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+ W_ci_estatus : out std_logic; -- estatus
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+ W_ci_ipending : out std_logic_vector(31 downto 0) -- ipending
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);
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end component nios2_uc_nios2;
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+ component fpoint_wrapper is
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+ generic (
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+ useDivider : integer := 0
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+ );
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+ port (
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+ clk : in std_logic := 'X'; -- clk
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+ clk_en : in std_logic := 'X'; -- clk_en
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+ dataa : in std_logic_vector(31 downto 0) := (others => 'X'); -- dataa
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+ datab : in std_logic_vector(31 downto 0) := (others => 'X'); -- datab
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+ n : in std_logic_vector(1 downto 0) := (others => 'X'); -- n
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+ reset : in std_logic := 'X'; -- reset
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+ start : in std_logic := 'X'; -- start
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+ done : out std_logic; -- done
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+ result : out std_logic_vector(31 downto 0) -- result
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+ );
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+ end component fpoint_wrapper;
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+
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component nios2_uc_onchip_memory2 is
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port (
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clk : in std_logic := 'X'; -- clk
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@@ -77,6 +134,16 @@ architecture rtl of nios2_uc is
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);
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end component nios2_uc_onchip_memory2;
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+ component nios2_uc_pio_BUTTON is
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+ port (
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+ clk : in std_logic := 'X'; -- clk
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+ reset_n : in std_logic := 'X'; -- reset_n
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+ address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
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+ readdata : out std_logic_vector(31 downto 0); -- readdata
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+ in_port : in std_logic_vector(7 downto 0) := (others => 'X') -- export
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+ );
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+ end component nios2_uc_pio_BUTTON;
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+
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component nios2_uc_pio_LED is
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port (
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clk : in std_logic := 'X'; -- clk
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@@ -90,6 +157,170 @@ architecture rtl of nios2_uc is
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);
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end component nios2_uc_pio_LED;
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+ component nios2_uc_pio_MATRIX is
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+ port (
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+ clk : in std_logic := 'X'; -- clk
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+ reset_n : in std_logic := 'X'; -- reset_n
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+ address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
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+ write_n : in std_logic := 'X'; -- write_n
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+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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+ chipselect : in std_logic := 'X'; -- chipselect
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+ readdata : out std_logic_vector(31 downto 0); -- readdata
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+ out_port : out std_logic_vector(19 downto 0) -- export
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+ );
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+ end component nios2_uc_pio_MATRIX;
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+
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+ component altera_customins_master_translator is
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+ generic (
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+ SHARED_COMB_AND_MULTI : integer := 0
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+ );
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+ port (
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+ ci_slave_dataa : in std_logic_vector(31 downto 0) := (others => 'X'); -- dataa
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+ ci_slave_datab : in std_logic_vector(31 downto 0) := (others => 'X'); -- datab
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+ ci_slave_result : out std_logic_vector(31 downto 0); -- result
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+ ci_slave_n : in std_logic_vector(7 downto 0) := (others => 'X'); -- n
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+ ci_slave_readra : in std_logic := 'X'; -- readra
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+ ci_slave_readrb : in std_logic := 'X'; -- readrb
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+ ci_slave_writerc : in std_logic := 'X'; -- writerc
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+ ci_slave_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- a
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+ ci_slave_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- b
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+ ci_slave_c : in std_logic_vector(4 downto 0) := (others => 'X'); -- c
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+ ci_slave_ipending : in std_logic_vector(31 downto 0) := (others => 'X'); -- ipending
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+ ci_slave_estatus : in std_logic := 'X'; -- estatus
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+ ci_slave_multi_clk : in std_logic := 'X'; -- clk
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+ ci_slave_multi_reset : in std_logic := 'X'; -- reset
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+ ci_slave_multi_clken : in std_logic := 'X'; -- clk_en
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+ ci_slave_multi_reset_req : in std_logic := 'X'; -- reset_req
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+ ci_slave_multi_start : in std_logic := 'X'; -- start
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+ ci_slave_multi_done : out std_logic; -- done
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+ comb_ci_master_dataa : out std_logic_vector(31 downto 0); -- dataa
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+ comb_ci_master_datab : out std_logic_vector(31 downto 0); -- datab
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+ comb_ci_master_result : in std_logic_vector(31 downto 0) := (others => 'X'); -- result
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+ comb_ci_master_n : out std_logic_vector(7 downto 0); -- n
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+ comb_ci_master_readra : out std_logic; -- readra
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+ comb_ci_master_readrb : out std_logic; -- readrb
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+ comb_ci_master_writerc : out std_logic; -- writerc
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+ comb_ci_master_a : out std_logic_vector(4 downto 0); -- a
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+ comb_ci_master_b : out std_logic_vector(4 downto 0); -- b
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+ comb_ci_master_c : out std_logic_vector(4 downto 0); -- c
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+ comb_ci_master_ipending : out std_logic_vector(31 downto 0); -- ipending
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+ comb_ci_master_estatus : out std_logic; -- estatus
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+ multi_ci_master_clk : out std_logic; -- clk
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+ multi_ci_master_reset : out std_logic; -- reset
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+ multi_ci_master_clken : out std_logic; -- clk_en
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+ multi_ci_master_reset_req : out std_logic; -- reset_req
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+ multi_ci_master_start : out std_logic; -- start
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+ multi_ci_master_done : in std_logic := 'X'; -- done
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+ multi_ci_master_dataa : out std_logic_vector(31 downto 0); -- dataa
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+ multi_ci_master_datab : out std_logic_vector(31 downto 0); -- datab
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+ multi_ci_master_result : in std_logic_vector(31 downto 0) := (others => 'X'); -- result
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+ multi_ci_master_n : out std_logic_vector(7 downto 0); -- n
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+ multi_ci_master_readra : out std_logic; -- readra
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+ multi_ci_master_readrb : out std_logic; -- readrb
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+ multi_ci_master_writerc : out std_logic; -- writerc
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+ multi_ci_master_a : out std_logic_vector(4 downto 0); -- a
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+ multi_ci_master_b : out std_logic_vector(4 downto 0); -- b
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+ multi_ci_master_c : out std_logic_vector(4 downto 0); -- c
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+ ci_slave_multi_dataa : in std_logic_vector(31 downto 0) := (others => 'X'); -- multi_dataa
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+ ci_slave_multi_datab : in std_logic_vector(31 downto 0) := (others => 'X'); -- multi_datab
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+ ci_slave_multi_result : out std_logic_vector(31 downto 0); -- multi_result
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+ ci_slave_multi_n : in std_logic_vector(7 downto 0) := (others => 'X'); -- multi_n
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+ ci_slave_multi_readra : in std_logic := 'X'; -- multi_readra
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+ ci_slave_multi_readrb : in std_logic := 'X'; -- multi_readrb
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+ ci_slave_multi_writerc : in std_logic := 'X'; -- multi_writerc
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+ ci_slave_multi_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- multi_a
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+ ci_slave_multi_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- multi_b
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+ ci_slave_multi_c : in std_logic_vector(4 downto 0) := (others => 'X') -- multi_c
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+ );
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+ end component altera_customins_master_translator;
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+
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+ component nios2_uc_nios2_custom_instruction_master_multi_xconnect is
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+ port (
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+ ci_slave_dataa : in std_logic_vector(31 downto 0) := (others => 'X'); -- dataa
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+ ci_slave_datab : in std_logic_vector(31 downto 0) := (others => 'X'); -- datab
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+ ci_slave_result : out std_logic_vector(31 downto 0); -- result
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+ ci_slave_n : in std_logic_vector(7 downto 0) := (others => 'X'); -- n
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+ ci_slave_readra : in std_logic := 'X'; -- readra
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+ ci_slave_readrb : in std_logic := 'X'; -- readrb
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+ ci_slave_writerc : in std_logic := 'X'; -- writerc
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+ ci_slave_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- a
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+ ci_slave_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- b
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+ ci_slave_c : in std_logic_vector(4 downto 0) := (others => 'X'); -- c
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+ ci_slave_ipending : in std_logic_vector(31 downto 0) := (others => 'X'); -- ipending
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+ ci_slave_estatus : in std_logic := 'X'; -- estatus
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+ ci_slave_clk : in std_logic := 'X'; -- clk
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+ ci_slave_reset : in std_logic := 'X'; -- reset
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+ ci_slave_clken : in std_logic := 'X'; -- clk_en
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+ ci_slave_reset_req : in std_logic := 'X'; -- reset_req
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+ ci_slave_start : in std_logic := 'X'; -- start
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+ ci_slave_done : out std_logic; -- done
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+ ci_master0_dataa : out std_logic_vector(31 downto 0); -- dataa
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+ ci_master0_datab : out std_logic_vector(31 downto 0); -- datab
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+ ci_master0_result : in std_logic_vector(31 downto 0) := (others => 'X'); -- result
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+ ci_master0_n : out std_logic_vector(7 downto 0); -- n
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+ ci_master0_readra : out std_logic; -- readra
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+ ci_master0_readrb : out std_logic; -- readrb
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+ ci_master0_writerc : out std_logic; -- writerc
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+ ci_master0_a : out std_logic_vector(4 downto 0); -- a
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+ ci_master0_b : out std_logic_vector(4 downto 0); -- b
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+ ci_master0_c : out std_logic_vector(4 downto 0); -- c
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+ ci_master0_ipending : out std_logic_vector(31 downto 0); -- ipending
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+ ci_master0_estatus : out std_logic; -- estatus
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+ ci_master0_clk : out std_logic; -- clk
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+ ci_master0_reset : out std_logic; -- reset
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+ ci_master0_clken : out std_logic; -- clk_en
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+ ci_master0_reset_req : out std_logic; -- reset_req
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+ ci_master0_start : out std_logic; -- start
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+ ci_master0_done : in std_logic := 'X' -- done
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+ );
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+ end component nios2_uc_nios2_custom_instruction_master_multi_xconnect;
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+
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+ component altera_customins_slave_translator is
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+ generic (
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+ N_WIDTH : integer := 8;
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+ USE_DONE : integer := 1;
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+ NUM_FIXED_CYCLES : integer := 2
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+ );
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+ port (
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+ ci_slave_dataa : in std_logic_vector(31 downto 0) := (others => 'X'); -- dataa
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+ ci_slave_datab : in std_logic_vector(31 downto 0) := (others => 'X'); -- datab
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+ ci_slave_result : out std_logic_vector(31 downto 0); -- result
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+ ci_slave_n : in std_logic_vector(7 downto 0) := (others => 'X'); -- n
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+ ci_slave_readra : in std_logic := 'X'; -- readra
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+ ci_slave_readrb : in std_logic := 'X'; -- readrb
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+ ci_slave_writerc : in std_logic := 'X'; -- writerc
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+ ci_slave_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- a
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+ ci_slave_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- b
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+ ci_slave_c : in std_logic_vector(4 downto 0) := (others => 'X'); -- c
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+ ci_slave_ipending : in std_logic_vector(31 downto 0) := (others => 'X'); -- ipending
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+ ci_slave_estatus : in std_logic := 'X'; -- estatus
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+ ci_slave_clk : in std_logic := 'X'; -- clk
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+ ci_slave_clken : in std_logic := 'X'; -- clk_en
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+ ci_slave_reset_req : in std_logic := 'X'; -- reset_req
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+ ci_slave_reset : in std_logic := 'X'; -- reset
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+ ci_slave_start : in std_logic := 'X'; -- start
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+ ci_slave_done : out std_logic; -- done
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+ ci_master_dataa : out std_logic_vector(31 downto 0); -- dataa
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+ ci_master_datab : out std_logic_vector(31 downto 0); -- datab
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+ ci_master_result : in std_logic_vector(31 downto 0) := (others => 'X'); -- result
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+ ci_master_n : out std_logic_vector(1 downto 0); -- n
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+ ci_master_clk : out std_logic; -- clk
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+ ci_master_clken : out std_logic; -- clk_en
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+ ci_master_reset : out std_logic; -- reset
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+ ci_master_start : out std_logic; -- start
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+ ci_master_done : in std_logic := 'X'; -- done
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+ ci_master_readra : out std_logic; -- readra
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+ ci_master_readrb : out std_logic; -- readrb
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+ ci_master_writerc : out std_logic; -- writerc
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+ ci_master_a : out std_logic_vector(4 downto 0); -- a
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+ ci_master_b : out std_logic_vector(4 downto 0); -- b
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+ ci_master_c : out std_logic_vector(4 downto 0); -- c
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+ ci_master_ipending : out std_logic_vector(31 downto 0); -- ipending
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+ ci_master_estatus : out std_logic; -- estatus
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+ ci_master_reset_req : out std_logic -- reset_req
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+ );
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+ end component altera_customins_slave_translator;
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+
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component nios2_uc_mm_interconnect_0 is
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port (
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clk_50_clk_clk : in std_logic := 'X'; -- clk
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@@ -113,6 +344,12 @@ architecture rtl of nios2_uc is
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jtag_uart_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
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jtag_uart_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
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jtag_uart_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
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+ lcd_16207_control_slave_address : out std_logic_vector(1 downto 0); -- address
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+ lcd_16207_control_slave_write : out std_logic; -- write
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+ lcd_16207_control_slave_read : out std_logic; -- read
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+ lcd_16207_control_slave_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
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+ lcd_16207_control_slave_writedata : out std_logic_vector(7 downto 0); -- writedata
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+ lcd_16207_control_slave_begintransfer : out std_logic; -- begintransfer
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nios2_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
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nios2_debug_mem_slave_write : out std_logic; -- write
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nios2_debug_mem_slave_read : out std_logic; -- read
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@@ -128,11 +365,18 @@ architecture rtl of nios2_uc is
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onchip_memory2_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
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onchip_memory2_s1_chipselect : out std_logic; -- chipselect
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onchip_memory2_s1_clken : out std_logic; -- clken
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+ pio_BUTTON_s1_address : out std_logic_vector(1 downto 0); -- address
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+ pio_BUTTON_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
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pio_LED_s1_address : out std_logic_vector(1 downto 0); -- address
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pio_LED_s1_write : out std_logic; -- write
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pio_LED_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
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pio_LED_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
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- pio_LED_s1_chipselect : out std_logic -- chipselect
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+ pio_LED_s1_chipselect : out std_logic; -- chipselect
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+ pio_MATRIX_s1_address : out std_logic_vector(1 downto 0); -- address
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+ pio_MATRIX_s1_write : out std_logic; -- write
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+ pio_MATRIX_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
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+ pio_MATRIX_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
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+ pio_MATRIX_s1_chipselect : out std_logic -- chipselect
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);
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end component nios2_uc_mm_interconnect_0;
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@@ -211,55 +455,130 @@ architecture rtl of nios2_uc is
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);
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end component altera_reset_controller;
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- signal nios2_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_data_master_readdata -> nios2:d_readdata
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- signal nios2_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_data_master_waitrequest -> nios2:d_waitrequest
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- signal nios2_data_master_debugaccess : std_logic; -- nios2:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_data_master_debugaccess
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- signal nios2_data_master_address : std_logic_vector(19 downto 0); -- nios2:d_address -> mm_interconnect_0:nios2_data_master_address
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- signal nios2_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2:d_byteenable -> mm_interconnect_0:nios2_data_master_byteenable
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- signal nios2_data_master_read : std_logic; -- nios2:d_read -> mm_interconnect_0:nios2_data_master_read
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- signal nios2_data_master_write : std_logic; -- nios2:d_write -> mm_interconnect_0:nios2_data_master_write
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- signal nios2_data_master_writedata : std_logic_vector(31 downto 0); -- nios2:d_writedata -> mm_interconnect_0:nios2_data_master_writedata
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- signal nios2_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_instruction_master_readdata -> nios2:i_readdata
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- signal nios2_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_instruction_master_waitrequest -> nios2:i_waitrequest
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- signal nios2_instruction_master_address : std_logic_vector(19 downto 0); -- nios2:i_address -> mm_interconnect_0:nios2_instruction_master_address
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- signal nios2_instruction_master_read : std_logic; -- nios2:i_read -> mm_interconnect_0:nios2_instruction_master_read
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- signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
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- signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
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- signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
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- signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
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- signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_avalon_jtag_slave_read:in
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- signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_avalon_jtag_slave_write:in
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- signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
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- signal mm_interconnect_0_nios2_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2:debug_mem_slave_readdata -> mm_interconnect_0:nios2_debug_mem_slave_readdata
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- signal mm_interconnect_0_nios2_debug_mem_slave_waitrequest : std_logic; -- nios2:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_debug_mem_slave_waitrequest
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- signal mm_interconnect_0_nios2_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_debug_mem_slave_debugaccess -> nios2:debug_mem_slave_debugaccess
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- signal mm_interconnect_0_nios2_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_debug_mem_slave_address -> nios2:debug_mem_slave_address
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- signal mm_interconnect_0_nios2_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_debug_mem_slave_read -> nios2:debug_mem_slave_read
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- signal mm_interconnect_0_nios2_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_debug_mem_slave_byteenable -> nios2:debug_mem_slave_byteenable
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- signal mm_interconnect_0_nios2_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_debug_mem_slave_write -> nios2:debug_mem_slave_write
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- signal mm_interconnect_0_nios2_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_debug_mem_slave_writedata -> nios2:debug_mem_slave_writedata
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- signal mm_interconnect_0_onchip_memory2_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_s1_chipselect -> onchip_memory2:chipselect
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- signal mm_interconnect_0_onchip_memory2_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2:readdata -> mm_interconnect_0:onchip_memory2_s1_readdata
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- signal mm_interconnect_0_onchip_memory2_s1_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_memory2_s1_address -> onchip_memory2:address
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- signal mm_interconnect_0_onchip_memory2_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_s1_byteenable -> onchip_memory2:byteenable
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- signal mm_interconnect_0_onchip_memory2_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_s1_write -> onchip_memory2:write
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- signal mm_interconnect_0_onchip_memory2_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_s1_writedata -> onchip_memory2:writedata
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- signal mm_interconnect_0_onchip_memory2_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_s1_clken -> onchip_memory2:clken
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- signal mm_interconnect_0_pio_led_s1_chipselect : std_logic; -- mm_interconnect_0:pio_LED_s1_chipselect -> pio_LED:chipselect
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- signal mm_interconnect_0_pio_led_s1_readdata : std_logic_vector(31 downto 0); -- pio_LED:readdata -> mm_interconnect_0:pio_LED_s1_readdata
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- signal mm_interconnect_0_pio_led_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_LED_s1_address -> pio_LED:address
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- signal mm_interconnect_0_pio_led_s1_write : std_logic; -- mm_interconnect_0:pio_LED_s1_write -> mm_interconnect_0_pio_led_s1_write:in
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- signal mm_interconnect_0_pio_led_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_LED_s1_writedata -> pio_LED:writedata
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- signal irq_mapper_receiver0_irq : std_logic; -- jtag_uart:av_irq -> irq_mapper:receiver0_irq
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- signal nios2_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2:irq
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- signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_reset_reset_bridge_in_reset_reset, onchip_memory2:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
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- signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [nios2:reset_req, onchip_memory2:reset_req, rst_translator:reset_req_in]
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- signal nios2_debug_reset_request_reset : std_logic; -- nios2:debug_reset_request -> rst_controller:reset_in1
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- signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> rst_controller:reset_in0
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- signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_avalon_jtag_slave_read:inv -> jtag_uart:av_read_n
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- signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_avalon_jtag_slave_write:inv -> jtag_uart:av_write_n
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- signal mm_interconnect_0_pio_led_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_led_s1_write:inv -> pio_LED:write_n
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- signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [jtag_uart:rst_n, nios2:reset_n, pio_LED:reset_n]
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+ signal nios2_custom_instruction_master_readra : std_logic; -- nios2:D_ci_readra -> nios2_custom_instruction_master_translator:ci_slave_readra
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+ signal nios2_custom_instruction_master_a : std_logic_vector(4 downto 0); -- nios2:D_ci_a -> nios2_custom_instruction_master_translator:ci_slave_a
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+ signal nios2_custom_instruction_master_b : std_logic_vector(4 downto 0); -- nios2:D_ci_b -> nios2_custom_instruction_master_translator:ci_slave_b
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+ signal nios2_custom_instruction_master_c : std_logic_vector(4 downto 0); -- nios2:D_ci_c -> nios2_custom_instruction_master_translator:ci_slave_c
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+ signal nios2_custom_instruction_master_readrb : std_logic; -- nios2:D_ci_readrb -> nios2_custom_instruction_master_translator:ci_slave_readrb
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+ signal nios2_custom_instruction_master_clk : std_logic; -- nios2:E_ci_multi_clock -> nios2_custom_instruction_master_translator:ci_slave_multi_clk
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+ signal nios2_custom_instruction_master_ipending : std_logic_vector(31 downto 0); -- nios2:W_ci_ipending -> nios2_custom_instruction_master_translator:ci_slave_ipending
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+ signal nios2_custom_instruction_master_start : std_logic; -- nios2:E_ci_multi_start -> nios2_custom_instruction_master_translator:ci_slave_multi_start
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+ signal nios2_custom_instruction_master_reset_req : std_logic; -- nios2:E_ci_multi_reset_req -> nios2_custom_instruction_master_translator:ci_slave_multi_reset_req
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+ signal nios2_custom_instruction_master_done : std_logic; -- nios2_custom_instruction_master_translator:ci_slave_multi_done -> nios2:E_ci_multi_done
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+ signal nios2_custom_instruction_master_n : std_logic_vector(7 downto 0); -- nios2:D_ci_n -> nios2_custom_instruction_master_translator:ci_slave_n
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+ signal nios2_custom_instruction_master_result : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_translator:ci_slave_result -> nios2:E_ci_result
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+ signal nios2_custom_instruction_master_estatus : std_logic; -- nios2:W_ci_estatus -> nios2_custom_instruction_master_translator:ci_slave_estatus
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+ signal nios2_custom_instruction_master_clk_en : std_logic; -- nios2:E_ci_multi_clk_en -> nios2_custom_instruction_master_translator:ci_slave_multi_clken
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+ signal nios2_custom_instruction_master_datab : std_logic_vector(31 downto 0); -- nios2:E_ci_datab -> nios2_custom_instruction_master_translator:ci_slave_datab
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+ signal nios2_custom_instruction_master_dataa : std_logic_vector(31 downto 0); -- nios2:E_ci_dataa -> nios2_custom_instruction_master_translator:ci_slave_dataa
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+ signal nios2_custom_instruction_master_reset : std_logic; -- nios2:E_ci_multi_reset -> nios2_custom_instruction_master_translator:ci_slave_multi_reset
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+ signal nios2_custom_instruction_master_writerc : std_logic; -- nios2:D_ci_writerc -> nios2_custom_instruction_master_translator:ci_slave_writerc
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_readra : std_logic; -- nios2_custom_instruction_master_translator:multi_ci_master_readra -> nios2_custom_instruction_master_multi_xconnect:ci_slave_readra
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_a : std_logic_vector(4 downto 0); -- nios2_custom_instruction_master_translator:multi_ci_master_a -> nios2_custom_instruction_master_multi_xconnect:ci_slave_a
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_b : std_logic_vector(4 downto 0); -- nios2_custom_instruction_master_translator:multi_ci_master_b -> nios2_custom_instruction_master_multi_xconnect:ci_slave_b
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_clk : std_logic; -- nios2_custom_instruction_master_translator:multi_ci_master_clk -> nios2_custom_instruction_master_multi_xconnect:ci_slave_clk
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_readrb : std_logic; -- nios2_custom_instruction_master_translator:multi_ci_master_readrb -> nios2_custom_instruction_master_multi_xconnect:ci_slave_readrb
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_c : std_logic_vector(4 downto 0); -- nios2_custom_instruction_master_translator:multi_ci_master_c -> nios2_custom_instruction_master_multi_xconnect:ci_slave_c
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_start : std_logic; -- nios2_custom_instruction_master_translator:multi_ci_master_start -> nios2_custom_instruction_master_multi_xconnect:ci_slave_start
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_reset_req : std_logic; -- nios2_custom_instruction_master_translator:multi_ci_master_reset_req -> nios2_custom_instruction_master_multi_xconnect:ci_slave_reset_req
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_done : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_slave_done -> nios2_custom_instruction_master_translator:multi_ci_master_done
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_n : std_logic_vector(7 downto 0); -- nios2_custom_instruction_master_translator:multi_ci_master_n -> nios2_custom_instruction_master_multi_xconnect:ci_slave_n
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_result : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_multi_xconnect:ci_slave_result -> nios2_custom_instruction_master_translator:multi_ci_master_result
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_clk_en : std_logic; -- nios2_custom_instruction_master_translator:multi_ci_master_clken -> nios2_custom_instruction_master_multi_xconnect:ci_slave_clken
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_datab : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_translator:multi_ci_master_datab -> nios2_custom_instruction_master_multi_xconnect:ci_slave_datab
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_dataa : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_translator:multi_ci_master_dataa -> nios2_custom_instruction_master_multi_xconnect:ci_slave_dataa
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_reset : std_logic; -- nios2_custom_instruction_master_translator:multi_ci_master_reset -> nios2_custom_instruction_master_multi_xconnect:ci_slave_reset
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+ signal nios2_custom_instruction_master_translator_multi_ci_master_writerc : std_logic; -- nios2_custom_instruction_master_translator:multi_ci_master_writerc -> nios2_custom_instruction_master_multi_xconnect:ci_slave_writerc
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_readra : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_master0_readra -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_readra
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_a : std_logic_vector(4 downto 0); -- nios2_custom_instruction_master_multi_xconnect:ci_master0_a -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_a
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_b : std_logic_vector(4 downto 0); -- nios2_custom_instruction_master_multi_xconnect:ci_master0_b -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_b
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_readrb : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_master0_readrb -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_readrb
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_c : std_logic_vector(4 downto 0); -- nios2_custom_instruction_master_multi_xconnect:ci_master0_c -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_c
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_clk : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_master0_clk -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_clk
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_ipending : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_multi_xconnect:ci_master0_ipending -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_ipending
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_start : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_master0_start -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_start
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_reset_req : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_master0_reset_req -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_reset_req
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_done : std_logic; -- nios2_custom_instruction_master_multi_slave_translator0:ci_slave_done -> nios2_custom_instruction_master_multi_xconnect:ci_master0_done
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_n : std_logic_vector(7 downto 0); -- nios2_custom_instruction_master_multi_xconnect:ci_master0_n -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_n
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_result : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_multi_slave_translator0:ci_slave_result -> nios2_custom_instruction_master_multi_xconnect:ci_master0_result
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_estatus : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_master0_estatus -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_estatus
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_clk_en : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_master0_clken -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_clken
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_datab : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_multi_xconnect:ci_master0_datab -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_datab
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_dataa : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_multi_xconnect:ci_master0_dataa -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_dataa
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_reset : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_master0_reset -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_reset
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+ signal nios2_custom_instruction_master_multi_xconnect_ci_master0_writerc : std_logic; -- nios2_custom_instruction_master_multi_xconnect:ci_master0_writerc -> nios2_custom_instruction_master_multi_slave_translator0:ci_slave_writerc
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+ signal nios2_custom_instruction_master_multi_slave_translator0_ci_master_result : std_logic_vector(31 downto 0); -- nios_custom_instr_floating_point_0:result -> nios2_custom_instruction_master_multi_slave_translator0:ci_master_result
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+ signal nios2_custom_instruction_master_multi_slave_translator0_ci_master_clk : std_logic; -- nios2_custom_instruction_master_multi_slave_translator0:ci_master_clk -> nios_custom_instr_floating_point_0:clk
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+ signal nios2_custom_instruction_master_multi_slave_translator0_ci_master_clk_en : std_logic; -- nios2_custom_instruction_master_multi_slave_translator0:ci_master_clken -> nios_custom_instr_floating_point_0:clk_en
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+ signal nios2_custom_instruction_master_multi_slave_translator0_ci_master_datab : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_multi_slave_translator0:ci_master_datab -> nios_custom_instr_floating_point_0:datab
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+ signal nios2_custom_instruction_master_multi_slave_translator0_ci_master_dataa : std_logic_vector(31 downto 0); -- nios2_custom_instruction_master_multi_slave_translator0:ci_master_dataa -> nios_custom_instr_floating_point_0:dataa
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+ signal nios2_custom_instruction_master_multi_slave_translator0_ci_master_start : std_logic; -- nios2_custom_instruction_master_multi_slave_translator0:ci_master_start -> nios_custom_instr_floating_point_0:start
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+ signal nios2_custom_instruction_master_multi_slave_translator0_ci_master_reset : std_logic; -- nios2_custom_instruction_master_multi_slave_translator0:ci_master_reset -> nios_custom_instr_floating_point_0:reset
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+ signal nios2_custom_instruction_master_multi_slave_translator0_ci_master_done : std_logic; -- nios_custom_instr_floating_point_0:done -> nios2_custom_instruction_master_multi_slave_translator0:ci_master_done
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+ signal nios2_custom_instruction_master_multi_slave_translator0_ci_master_n : std_logic_vector(1 downto 0); -- nios2_custom_instruction_master_multi_slave_translator0:ci_master_n -> nios_custom_instr_floating_point_0:n
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+ signal nios2_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_data_master_readdata -> nios2:d_readdata
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+ signal nios2_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_data_master_waitrequest -> nios2:d_waitrequest
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+ signal nios2_data_master_debugaccess : std_logic; -- nios2:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_data_master_debugaccess
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+ signal nios2_data_master_address : std_logic_vector(19 downto 0); -- nios2:d_address -> mm_interconnect_0:nios2_data_master_address
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+ signal nios2_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2:d_byteenable -> mm_interconnect_0:nios2_data_master_byteenable
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+ signal nios2_data_master_read : std_logic; -- nios2:d_read -> mm_interconnect_0:nios2_data_master_read
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+ signal nios2_data_master_write : std_logic; -- nios2:d_write -> mm_interconnect_0:nios2_data_master_write
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+ signal nios2_data_master_writedata : std_logic_vector(31 downto 0); -- nios2:d_writedata -> mm_interconnect_0:nios2_data_master_writedata
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+ signal nios2_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_instruction_master_readdata -> nios2:i_readdata
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+ signal nios2_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_instruction_master_waitrequest -> nios2:i_waitrequest
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+ signal nios2_instruction_master_address : std_logic_vector(19 downto 0); -- nios2:i_address -> mm_interconnect_0:nios2_instruction_master_address
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+ signal nios2_instruction_master_read : std_logic; -- nios2:i_read -> mm_interconnect_0:nios2_instruction_master_read
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+ signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
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+ signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
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+ signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
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+ signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
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+ signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_avalon_jtag_slave_read:in
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+ signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_avalon_jtag_slave_write:in
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+ signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
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+ signal mm_interconnect_0_lcd_16207_control_slave_readdata : std_logic_vector(7 downto 0); -- lcd_16207:readdata -> mm_interconnect_0:lcd_16207_control_slave_readdata
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+ signal mm_interconnect_0_lcd_16207_control_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:lcd_16207_control_slave_address -> lcd_16207:address
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+ signal mm_interconnect_0_lcd_16207_control_slave_read : std_logic; -- mm_interconnect_0:lcd_16207_control_slave_read -> lcd_16207:read
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+ signal mm_interconnect_0_lcd_16207_control_slave_begintransfer : std_logic; -- mm_interconnect_0:lcd_16207_control_slave_begintransfer -> lcd_16207:begintransfer
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+ signal mm_interconnect_0_lcd_16207_control_slave_write : std_logic; -- mm_interconnect_0:lcd_16207_control_slave_write -> lcd_16207:write
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+ signal mm_interconnect_0_lcd_16207_control_slave_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:lcd_16207_control_slave_writedata -> lcd_16207:writedata
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+ signal mm_interconnect_0_nios2_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2:debug_mem_slave_readdata -> mm_interconnect_0:nios2_debug_mem_slave_readdata
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+ signal mm_interconnect_0_nios2_debug_mem_slave_waitrequest : std_logic; -- nios2:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_debug_mem_slave_waitrequest
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+ signal mm_interconnect_0_nios2_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_debug_mem_slave_debugaccess -> nios2:debug_mem_slave_debugaccess
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+ signal mm_interconnect_0_nios2_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_debug_mem_slave_address -> nios2:debug_mem_slave_address
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+ signal mm_interconnect_0_nios2_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_debug_mem_slave_read -> nios2:debug_mem_slave_read
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+ signal mm_interconnect_0_nios2_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_debug_mem_slave_byteenable -> nios2:debug_mem_slave_byteenable
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+ signal mm_interconnect_0_nios2_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_debug_mem_slave_write -> nios2:debug_mem_slave_write
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+ signal mm_interconnect_0_nios2_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_debug_mem_slave_writedata -> nios2:debug_mem_slave_writedata
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+ signal mm_interconnect_0_onchip_memory2_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_s1_chipselect -> onchip_memory2:chipselect
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+ signal mm_interconnect_0_onchip_memory2_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2:readdata -> mm_interconnect_0:onchip_memory2_s1_readdata
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+ signal mm_interconnect_0_onchip_memory2_s1_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_memory2_s1_address -> onchip_memory2:address
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+ signal mm_interconnect_0_onchip_memory2_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_s1_byteenable -> onchip_memory2:byteenable
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+ signal mm_interconnect_0_onchip_memory2_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_s1_write -> onchip_memory2:write
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+ signal mm_interconnect_0_onchip_memory2_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_s1_writedata -> onchip_memory2:writedata
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+ signal mm_interconnect_0_onchip_memory2_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_s1_clken -> onchip_memory2:clken
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+ signal mm_interconnect_0_pio_led_s1_chipselect : std_logic; -- mm_interconnect_0:pio_LED_s1_chipselect -> pio_LED:chipselect
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+ signal mm_interconnect_0_pio_led_s1_readdata : std_logic_vector(31 downto 0); -- pio_LED:readdata -> mm_interconnect_0:pio_LED_s1_readdata
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+ signal mm_interconnect_0_pio_led_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_LED_s1_address -> pio_LED:address
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+ signal mm_interconnect_0_pio_led_s1_write : std_logic; -- mm_interconnect_0:pio_LED_s1_write -> mm_interconnect_0_pio_led_s1_write:in
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+ signal mm_interconnect_0_pio_led_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_LED_s1_writedata -> pio_LED:writedata
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+ signal mm_interconnect_0_pio_matrix_s1_chipselect : std_logic; -- mm_interconnect_0:pio_MATRIX_s1_chipselect -> pio_MATRIX:chipselect
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+ signal mm_interconnect_0_pio_matrix_s1_readdata : std_logic_vector(31 downto 0); -- pio_MATRIX:readdata -> mm_interconnect_0:pio_MATRIX_s1_readdata
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+ signal mm_interconnect_0_pio_matrix_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_MATRIX_s1_address -> pio_MATRIX:address
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+ signal mm_interconnect_0_pio_matrix_s1_write : std_logic; -- mm_interconnect_0:pio_MATRIX_s1_write -> mm_interconnect_0_pio_matrix_s1_write:in
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+ signal mm_interconnect_0_pio_matrix_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_MATRIX_s1_writedata -> pio_MATRIX:writedata
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+ signal mm_interconnect_0_pio_button_s1_readdata : std_logic_vector(31 downto 0); -- pio_BUTTON:readdata -> mm_interconnect_0:pio_BUTTON_s1_readdata
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+ signal mm_interconnect_0_pio_button_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_BUTTON_s1_address -> pio_BUTTON:address
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+ signal irq_mapper_receiver0_irq : std_logic; -- jtag_uart:av_irq -> irq_mapper:receiver0_irq
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+ signal nios2_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2:irq
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+ signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_reset_reset_bridge_in_reset_reset, onchip_memory2:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
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+ signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [nios2:reset_req, onchip_memory2:reset_req, rst_translator:reset_req_in]
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+ signal nios2_debug_reset_request_reset : std_logic; -- nios2:debug_reset_request -> rst_controller:reset_in1
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+ signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> rst_controller:reset_in0
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+ signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_avalon_jtag_slave_read:inv -> jtag_uart:av_read_n
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+ signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_avalon_jtag_slave_write:inv -> jtag_uart:av_write_n
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+ signal mm_interconnect_0_pio_led_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_led_s1_write:inv -> pio_LED:write_n
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+ signal mm_interconnect_0_pio_matrix_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_matrix_s1_write:inv -> pio_MATRIX:write_n
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+ signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [jtag_uart:rst_n, lcd_16207:reset_n, nios2:reset_n, pio_BUTTON:reset_n, pio_LED:reset_n, pio_MATRIX:reset_n]
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begin
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@@ -277,6 +596,22 @@ begin
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av_irq => irq_mapper_receiver0_irq -- irq.irq
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);
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+ lcd_16207 : component nios2_uc_lcd_16207
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+ port map (
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+ reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
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+ clk => clk_clk, -- clk.clk
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+ begintransfer => mm_interconnect_0_lcd_16207_control_slave_begintransfer, -- control_slave.begintransfer
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+ read => mm_interconnect_0_lcd_16207_control_slave_read, -- .read
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+ write => mm_interconnect_0_lcd_16207_control_slave_write, -- .write
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+ readdata => mm_interconnect_0_lcd_16207_control_slave_readdata, -- .readdata
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+ writedata => mm_interconnect_0_lcd_16207_control_slave_writedata, -- .writedata
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+ address => mm_interconnect_0_lcd_16207_control_slave_address, -- .address
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+ LCD_RS => lcd_16207_ext_RS, -- external.export
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+ LCD_RW => lcd_16207_ext_RW, -- .export
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+ LCD_data => lcd_16207_ext_data, -- .export
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+ LCD_E => lcd_16207_ext_E -- .export
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+ );
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+
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nios2 : component nios2_uc_nios2
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port map (
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clk => clk_clk, -- clk.clk
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@@ -304,7 +639,40 @@ begin
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debug_mem_slave_waitrequest => mm_interconnect_0_nios2_debug_mem_slave_waitrequest, -- .waitrequest
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debug_mem_slave_write => mm_interconnect_0_nios2_debug_mem_slave_write, -- .write
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debug_mem_slave_writedata => mm_interconnect_0_nios2_debug_mem_slave_writedata, -- .writedata
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- dummy_ci_port => open -- custom_instruction_master.readra
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+ E_ci_multi_done => nios2_custom_instruction_master_done, -- custom_instruction_master.done
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+ E_ci_multi_clk_en => nios2_custom_instruction_master_clk_en, -- .clk_en
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+ E_ci_multi_start => nios2_custom_instruction_master_start, -- .start
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+ E_ci_result => nios2_custom_instruction_master_result, -- .result
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+ D_ci_a => nios2_custom_instruction_master_a, -- .a
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+ D_ci_b => nios2_custom_instruction_master_b, -- .b
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+ D_ci_c => nios2_custom_instruction_master_c, -- .c
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+ D_ci_n => nios2_custom_instruction_master_n, -- .n
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+ D_ci_readra => nios2_custom_instruction_master_readra, -- .readra
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+ D_ci_readrb => nios2_custom_instruction_master_readrb, -- .readrb
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+ D_ci_writerc => nios2_custom_instruction_master_writerc, -- .writerc
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+ E_ci_dataa => nios2_custom_instruction_master_dataa, -- .dataa
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+ E_ci_datab => nios2_custom_instruction_master_datab, -- .datab
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+ E_ci_multi_clock => nios2_custom_instruction_master_clk, -- .clk
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+ E_ci_multi_reset => nios2_custom_instruction_master_reset, -- .reset
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+ E_ci_multi_reset_req => nios2_custom_instruction_master_reset_req, -- .reset_req
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+ W_ci_estatus => nios2_custom_instruction_master_estatus, -- .estatus
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+ W_ci_ipending => nios2_custom_instruction_master_ipending -- .ipending
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+ );
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+
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+ nios_custom_instr_floating_point_0 : component fpoint_wrapper
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+ generic map (
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+ useDivider => 1
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+ )
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+ port map (
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+ clk => nios2_custom_instruction_master_multi_slave_translator0_ci_master_clk, -- s1.clk
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+ clk_en => nios2_custom_instruction_master_multi_slave_translator0_ci_master_clk_en, -- .clk_en
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+ dataa => nios2_custom_instruction_master_multi_slave_translator0_ci_master_dataa, -- .dataa
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+ datab => nios2_custom_instruction_master_multi_slave_translator0_ci_master_datab, -- .datab
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+ n => nios2_custom_instruction_master_multi_slave_translator0_ci_master_n, -- .n
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+ reset => nios2_custom_instruction_master_multi_slave_translator0_ci_master_reset, -- .reset
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+ start => nios2_custom_instruction_master_multi_slave_translator0_ci_master_start, -- .start
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+ done => nios2_custom_instruction_master_multi_slave_translator0_ci_master_done, -- .done
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+ result => nios2_custom_instruction_master_multi_slave_translator0_ci_master_result -- .result
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);
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onchip_memory2 : component nios2_uc_onchip_memory2
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@@ -322,6 +690,15 @@ begin
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freeze => '0' -- (terminated)
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);
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+ pio_button : component nios2_uc_pio_BUTTON
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+ port map (
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+ clk => clk_clk, -- clk.clk
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+ reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
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+ address => mm_interconnect_0_pio_button_s1_address, -- s1.address
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+ readdata => mm_interconnect_0_pio_button_s1_readdata, -- .readdata
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+ in_port => pio_button_ext_conn_export -- external_connection.export
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+ );
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+
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pio_led : component nios2_uc_pio_LED
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port map (
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clk => clk_clk, -- clk.clk
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@@ -334,6 +711,166 @@ begin
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out_port => pio_led_ext_conn_export -- external_connection.export
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);
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+ pio_matrix : component nios2_uc_pio_MATRIX
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+ port map (
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+ clk => clk_clk, -- clk.clk
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+ reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
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+ address => mm_interconnect_0_pio_matrix_s1_address, -- s1.address
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+ write_n => mm_interconnect_0_pio_matrix_s1_write_ports_inv, -- .write_n
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+ writedata => mm_interconnect_0_pio_matrix_s1_writedata, -- .writedata
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+ chipselect => mm_interconnect_0_pio_matrix_s1_chipselect, -- .chipselect
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+ readdata => mm_interconnect_0_pio_matrix_s1_readdata, -- .readdata
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+ out_port => pio_matrix_ext_conn_export -- external_connection.export
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+ );
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+
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+ nios2_custom_instruction_master_translator : component altera_customins_master_translator
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+ generic map (
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+ SHARED_COMB_AND_MULTI => 1
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+ )
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+ port map (
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+ ci_slave_dataa => nios2_custom_instruction_master_dataa, -- ci_slave.dataa
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+ ci_slave_datab => nios2_custom_instruction_master_datab, -- .datab
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+ ci_slave_result => nios2_custom_instruction_master_result, -- .result
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+ ci_slave_n => nios2_custom_instruction_master_n, -- .n
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+ ci_slave_readra => nios2_custom_instruction_master_readra, -- .readra
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+ ci_slave_readrb => nios2_custom_instruction_master_readrb, -- .readrb
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+ ci_slave_writerc => nios2_custom_instruction_master_writerc, -- .writerc
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+ ci_slave_a => nios2_custom_instruction_master_a, -- .a
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+ ci_slave_b => nios2_custom_instruction_master_b, -- .b
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+ ci_slave_c => nios2_custom_instruction_master_c, -- .c
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+ ci_slave_ipending => nios2_custom_instruction_master_ipending, -- .ipending
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+ ci_slave_estatus => nios2_custom_instruction_master_estatus, -- .estatus
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+ ci_slave_multi_clk => nios2_custom_instruction_master_clk, -- .clk
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+ ci_slave_multi_reset => nios2_custom_instruction_master_reset, -- .reset
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+ ci_slave_multi_clken => nios2_custom_instruction_master_clk_en, -- .clk_en
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+ ci_slave_multi_reset_req => nios2_custom_instruction_master_reset_req, -- .reset_req
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+ ci_slave_multi_start => nios2_custom_instruction_master_start, -- .start
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+ ci_slave_multi_done => nios2_custom_instruction_master_done, -- .done
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+ comb_ci_master_dataa => open, -- comb_ci_master.dataa
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+ comb_ci_master_datab => open, -- .datab
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+ comb_ci_master_result => open, -- .result
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+ comb_ci_master_n => open, -- .n
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+ comb_ci_master_readra => open, -- .readra
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+ comb_ci_master_readrb => open, -- .readrb
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+ comb_ci_master_writerc => open, -- .writerc
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+ comb_ci_master_a => open, -- .a
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+ comb_ci_master_b => open, -- .b
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+ comb_ci_master_c => open, -- .c
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+ comb_ci_master_ipending => open, -- .ipending
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+ comb_ci_master_estatus => open, -- .estatus
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+ multi_ci_master_clk => nios2_custom_instruction_master_translator_multi_ci_master_clk, -- multi_ci_master.clk
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+ multi_ci_master_reset => nios2_custom_instruction_master_translator_multi_ci_master_reset, -- .reset
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+ multi_ci_master_clken => nios2_custom_instruction_master_translator_multi_ci_master_clk_en, -- .clk_en
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+ multi_ci_master_reset_req => nios2_custom_instruction_master_translator_multi_ci_master_reset_req, -- .reset_req
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+ multi_ci_master_start => nios2_custom_instruction_master_translator_multi_ci_master_start, -- .start
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+ multi_ci_master_done => nios2_custom_instruction_master_translator_multi_ci_master_done, -- .done
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+ multi_ci_master_dataa => nios2_custom_instruction_master_translator_multi_ci_master_dataa, -- .dataa
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+ multi_ci_master_datab => nios2_custom_instruction_master_translator_multi_ci_master_datab, -- .datab
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+ multi_ci_master_result => nios2_custom_instruction_master_translator_multi_ci_master_result, -- .result
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+ multi_ci_master_n => nios2_custom_instruction_master_translator_multi_ci_master_n, -- .n
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+ multi_ci_master_readra => nios2_custom_instruction_master_translator_multi_ci_master_readra, -- .readra
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+ multi_ci_master_readrb => nios2_custom_instruction_master_translator_multi_ci_master_readrb, -- .readrb
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+ multi_ci_master_writerc => nios2_custom_instruction_master_translator_multi_ci_master_writerc, -- .writerc
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+ multi_ci_master_a => nios2_custom_instruction_master_translator_multi_ci_master_a, -- .a
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+ multi_ci_master_b => nios2_custom_instruction_master_translator_multi_ci_master_b, -- .b
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+ multi_ci_master_c => nios2_custom_instruction_master_translator_multi_ci_master_c, -- .c
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+ ci_slave_multi_dataa => "00000000000000000000000000000000", -- (terminated)
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+ ci_slave_multi_datab => "00000000000000000000000000000000", -- (terminated)
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+ ci_slave_multi_result => open, -- (terminated)
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+ ci_slave_multi_n => "00000000", -- (terminated)
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+ ci_slave_multi_readra => '0', -- (terminated)
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+ ci_slave_multi_readrb => '0', -- (terminated)
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+ ci_slave_multi_writerc => '0', -- (terminated)
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+ ci_slave_multi_a => "00000", -- (terminated)
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+ ci_slave_multi_b => "00000", -- (terminated)
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+ ci_slave_multi_c => "00000" -- (terminated)
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+ );
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+
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+ nios2_custom_instruction_master_multi_xconnect : component nios2_uc_nios2_custom_instruction_master_multi_xconnect
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+ port map (
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+ ci_slave_dataa => nios2_custom_instruction_master_translator_multi_ci_master_dataa, -- ci_slave.dataa
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+ ci_slave_datab => nios2_custom_instruction_master_translator_multi_ci_master_datab, -- .datab
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+ ci_slave_result => nios2_custom_instruction_master_translator_multi_ci_master_result, -- .result
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+ ci_slave_n => nios2_custom_instruction_master_translator_multi_ci_master_n, -- .n
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+ ci_slave_readra => nios2_custom_instruction_master_translator_multi_ci_master_readra, -- .readra
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+ ci_slave_readrb => nios2_custom_instruction_master_translator_multi_ci_master_readrb, -- .readrb
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+ ci_slave_writerc => nios2_custom_instruction_master_translator_multi_ci_master_writerc, -- .writerc
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+ ci_slave_a => nios2_custom_instruction_master_translator_multi_ci_master_a, -- .a
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+ ci_slave_b => nios2_custom_instruction_master_translator_multi_ci_master_b, -- .b
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+ ci_slave_c => nios2_custom_instruction_master_translator_multi_ci_master_c, -- .c
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+ ci_slave_ipending => open, -- .ipending
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+ ci_slave_estatus => open, -- .estatus
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+ ci_slave_clk => nios2_custom_instruction_master_translator_multi_ci_master_clk, -- .clk
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+ ci_slave_reset => nios2_custom_instruction_master_translator_multi_ci_master_reset, -- .reset
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+ ci_slave_clken => nios2_custom_instruction_master_translator_multi_ci_master_clk_en, -- .clk_en
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+ ci_slave_reset_req => nios2_custom_instruction_master_translator_multi_ci_master_reset_req, -- .reset_req
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+ ci_slave_start => nios2_custom_instruction_master_translator_multi_ci_master_start, -- .start
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+ ci_slave_done => nios2_custom_instruction_master_translator_multi_ci_master_done, -- .done
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+ ci_master0_dataa => nios2_custom_instruction_master_multi_xconnect_ci_master0_dataa, -- ci_master0.dataa
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+ ci_master0_datab => nios2_custom_instruction_master_multi_xconnect_ci_master0_datab, -- .datab
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+ ci_master0_result => nios2_custom_instruction_master_multi_xconnect_ci_master0_result, -- .result
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+ ci_master0_n => nios2_custom_instruction_master_multi_xconnect_ci_master0_n, -- .n
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+ ci_master0_readra => nios2_custom_instruction_master_multi_xconnect_ci_master0_readra, -- .readra
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+ ci_master0_readrb => nios2_custom_instruction_master_multi_xconnect_ci_master0_readrb, -- .readrb
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+ ci_master0_writerc => nios2_custom_instruction_master_multi_xconnect_ci_master0_writerc, -- .writerc
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+ ci_master0_a => nios2_custom_instruction_master_multi_xconnect_ci_master0_a, -- .a
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+ ci_master0_b => nios2_custom_instruction_master_multi_xconnect_ci_master0_b, -- .b
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+ ci_master0_c => nios2_custom_instruction_master_multi_xconnect_ci_master0_c, -- .c
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+ ci_master0_ipending => nios2_custom_instruction_master_multi_xconnect_ci_master0_ipending, -- .ipending
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+ ci_master0_estatus => nios2_custom_instruction_master_multi_xconnect_ci_master0_estatus, -- .estatus
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+ ci_master0_clk => nios2_custom_instruction_master_multi_xconnect_ci_master0_clk, -- .clk
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+ ci_master0_reset => nios2_custom_instruction_master_multi_xconnect_ci_master0_reset, -- .reset
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+ ci_master0_clken => nios2_custom_instruction_master_multi_xconnect_ci_master0_clk_en, -- .clk_en
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+ ci_master0_reset_req => nios2_custom_instruction_master_multi_xconnect_ci_master0_reset_req, -- .reset_req
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+ ci_master0_start => nios2_custom_instruction_master_multi_xconnect_ci_master0_start, -- .start
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+ ci_master0_done => nios2_custom_instruction_master_multi_xconnect_ci_master0_done -- .done
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+ );
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+
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+ nios2_custom_instruction_master_multi_slave_translator0 : component altera_customins_slave_translator
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+ generic map (
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+ N_WIDTH => 2,
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+ USE_DONE => 1,
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+ NUM_FIXED_CYCLES => 1
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+ )
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+ port map (
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+ ci_slave_dataa => nios2_custom_instruction_master_multi_xconnect_ci_master0_dataa, -- ci_slave.dataa
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+ ci_slave_datab => nios2_custom_instruction_master_multi_xconnect_ci_master0_datab, -- .datab
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+ ci_slave_result => nios2_custom_instruction_master_multi_xconnect_ci_master0_result, -- .result
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+ ci_slave_n => nios2_custom_instruction_master_multi_xconnect_ci_master0_n, -- .n
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+ ci_slave_readra => nios2_custom_instruction_master_multi_xconnect_ci_master0_readra, -- .readra
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+ ci_slave_readrb => nios2_custom_instruction_master_multi_xconnect_ci_master0_readrb, -- .readrb
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+ ci_slave_writerc => nios2_custom_instruction_master_multi_xconnect_ci_master0_writerc, -- .writerc
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+ ci_slave_a => nios2_custom_instruction_master_multi_xconnect_ci_master0_a, -- .a
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+ ci_slave_b => nios2_custom_instruction_master_multi_xconnect_ci_master0_b, -- .b
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+ ci_slave_c => nios2_custom_instruction_master_multi_xconnect_ci_master0_c, -- .c
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+ ci_slave_ipending => nios2_custom_instruction_master_multi_xconnect_ci_master0_ipending, -- .ipending
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+ ci_slave_estatus => nios2_custom_instruction_master_multi_xconnect_ci_master0_estatus, -- .estatus
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+ ci_slave_clk => nios2_custom_instruction_master_multi_xconnect_ci_master0_clk, -- .clk
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+ ci_slave_clken => nios2_custom_instruction_master_multi_xconnect_ci_master0_clk_en, -- .clk_en
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+ ci_slave_reset_req => nios2_custom_instruction_master_multi_xconnect_ci_master0_reset_req, -- .reset_req
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+ ci_slave_reset => nios2_custom_instruction_master_multi_xconnect_ci_master0_reset, -- .reset
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+ ci_slave_start => nios2_custom_instruction_master_multi_xconnect_ci_master0_start, -- .start
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+ ci_slave_done => nios2_custom_instruction_master_multi_xconnect_ci_master0_done, -- .done
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+ ci_master_dataa => nios2_custom_instruction_master_multi_slave_translator0_ci_master_dataa, -- ci_master.dataa
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+ ci_master_datab => nios2_custom_instruction_master_multi_slave_translator0_ci_master_datab, -- .datab
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+ ci_master_result => nios2_custom_instruction_master_multi_slave_translator0_ci_master_result, -- .result
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+ ci_master_n => nios2_custom_instruction_master_multi_slave_translator0_ci_master_n, -- .n
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+ ci_master_clk => nios2_custom_instruction_master_multi_slave_translator0_ci_master_clk, -- .clk
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+ ci_master_clken => nios2_custom_instruction_master_multi_slave_translator0_ci_master_clk_en, -- .clk_en
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+ ci_master_reset => nios2_custom_instruction_master_multi_slave_translator0_ci_master_reset, -- .reset
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+ ci_master_start => nios2_custom_instruction_master_multi_slave_translator0_ci_master_start, -- .start
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+ ci_master_done => nios2_custom_instruction_master_multi_slave_translator0_ci_master_done, -- .done
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+ ci_master_readra => open, -- (terminated)
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+ ci_master_readrb => open, -- (terminated)
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+ ci_master_writerc => open, -- (terminated)
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+ ci_master_a => open, -- (terminated)
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+ ci_master_b => open, -- (terminated)
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+ ci_master_c => open, -- (terminated)
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+ ci_master_ipending => open, -- (terminated)
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+ ci_master_estatus => open, -- (terminated)
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+ ci_master_reset_req => open -- (terminated)
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+ );
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+
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mm_interconnect_0 : component nios2_uc_mm_interconnect_0
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port map (
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clk_50_clk_clk => clk_clk, -- clk_50_clk.clk
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@@ -357,6 +894,12 @@ begin
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jtag_uart_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata, -- .writedata
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jtag_uart_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest, -- .waitrequest
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jtag_uart_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect, -- .chipselect
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+ lcd_16207_control_slave_address => mm_interconnect_0_lcd_16207_control_slave_address, -- lcd_16207_control_slave.address
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+ lcd_16207_control_slave_write => mm_interconnect_0_lcd_16207_control_slave_write, -- .write
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+ lcd_16207_control_slave_read => mm_interconnect_0_lcd_16207_control_slave_read, -- .read
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+ lcd_16207_control_slave_readdata => mm_interconnect_0_lcd_16207_control_slave_readdata, -- .readdata
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+ lcd_16207_control_slave_writedata => mm_interconnect_0_lcd_16207_control_slave_writedata, -- .writedata
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+ lcd_16207_control_slave_begintransfer => mm_interconnect_0_lcd_16207_control_slave_begintransfer, -- .begintransfer
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nios2_debug_mem_slave_address => mm_interconnect_0_nios2_debug_mem_slave_address, -- nios2_debug_mem_slave.address
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nios2_debug_mem_slave_write => mm_interconnect_0_nios2_debug_mem_slave_write, -- .write
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nios2_debug_mem_slave_read => mm_interconnect_0_nios2_debug_mem_slave_read, -- .read
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@@ -372,11 +915,18 @@ begin
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onchip_memory2_s1_byteenable => mm_interconnect_0_onchip_memory2_s1_byteenable, -- .byteenable
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onchip_memory2_s1_chipselect => mm_interconnect_0_onchip_memory2_s1_chipselect, -- .chipselect
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onchip_memory2_s1_clken => mm_interconnect_0_onchip_memory2_s1_clken, -- .clken
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+ pio_BUTTON_s1_address => mm_interconnect_0_pio_button_s1_address, -- pio_BUTTON_s1.address
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+ pio_BUTTON_s1_readdata => mm_interconnect_0_pio_button_s1_readdata, -- .readdata
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pio_LED_s1_address => mm_interconnect_0_pio_led_s1_address, -- pio_LED_s1.address
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pio_LED_s1_write => mm_interconnect_0_pio_led_s1_write, -- .write
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pio_LED_s1_readdata => mm_interconnect_0_pio_led_s1_readdata, -- .readdata
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pio_LED_s1_writedata => mm_interconnect_0_pio_led_s1_writedata, -- .writedata
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- pio_LED_s1_chipselect => mm_interconnect_0_pio_led_s1_chipselect -- .chipselect
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+ pio_LED_s1_chipselect => mm_interconnect_0_pio_led_s1_chipselect, -- .chipselect
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+ pio_MATRIX_s1_address => mm_interconnect_0_pio_matrix_s1_address, -- pio_MATRIX_s1.address
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+ pio_MATRIX_s1_write => mm_interconnect_0_pio_matrix_s1_write, -- .write
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+ pio_MATRIX_s1_readdata => mm_interconnect_0_pio_matrix_s1_readdata, -- .readdata
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+ pio_MATRIX_s1_writedata => mm_interconnect_0_pio_matrix_s1_writedata, -- .writedata
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+ pio_MATRIX_s1_chipselect => mm_interconnect_0_pio_matrix_s1_chipselect -- .chipselect
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);
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irq_mapper : component nios2_uc_irq_mapper
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@@ -460,6 +1010,8 @@ begin
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mm_interconnect_0_pio_led_s1_write_ports_inv <= not mm_interconnect_0_pio_led_s1_write;
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+ mm_interconnect_0_pio_matrix_s1_write_ports_inv <= not mm_interconnect_0_pio_matrix_s1_write;
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+
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rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
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end architecture rtl; -- of nios2_uc
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subDesTagesMitExtraKaese