DE2-115-FPGA-Pong/.qsys_edit/preferences.xml

<?xml version="1.0" encoding="UTF-8"?>
<preferences>
 <debug showDebugMenu="0" />
 <systemtable filter="All Interfaces">
  <columns>
   <connections preferredWidth="47" />
   <irq preferredWidth="34" />
  </columns>
 </systemtable>
 <library expandedCategories="Library,Project" />
 <window width="1280" height="1024" x="1280" y="379" />
 <hdlexample language="VHDL" />
 <generation synthesis="VHDL" />
</preferences>