altera_reset_synchronizer.v 3.4 KB

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  1. // (C) 2001-2018 Intel Corporation. All rights reserved.
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  7. // Agreement, Intel FPGA IP License Agreement, or other applicable
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  11. // agreement for further details.
  12. // $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
  13. // $Revision: #1 $
  14. // $Date: 2018/07/18 $
  15. // $Author: psgswbuild $
  16. // -----------------------------------------------
  17. // Reset Synchronizer
  18. // -----------------------------------------------
  19. `timescale 1 ns / 1 ns
  20. module altera_reset_synchronizer
  21. #(
  22. parameter ASYNC_RESET = 1,
  23. parameter DEPTH = 2
  24. )
  25. (
  26. input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
  27. input clk,
  28. output reset_out
  29. );
  30. // -----------------------------------------------
  31. // Synchronizer register chain. We cannot reuse the
  32. // standard synchronizer in this implementation
  33. // because our timing constraints are different.
  34. //
  35. // Instead of cutting the timing path to the d-input
  36. // on the first flop we need to cut the aclr input.
  37. //
  38. // We omit the "preserve" attribute on the final
  39. // output register, so that the synthesis tool can
  40. // duplicate it where needed.
  41. // -----------------------------------------------
  42. (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
  43. reg altera_reset_synchronizer_int_chain_out;
  44. generate if (ASYNC_RESET) begin
  45. // -----------------------------------------------
  46. // Assert asynchronously, deassert synchronously.
  47. // -----------------------------------------------
  48. always @(posedge clk or posedge reset_in) begin
  49. if (reset_in) begin
  50. altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
  51. altera_reset_synchronizer_int_chain_out <= 1'b1;
  52. end
  53. else begin
  54. altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
  55. altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
  56. altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
  57. end
  58. end
  59. assign reset_out = altera_reset_synchronizer_int_chain_out;
  60. end else begin
  61. // -----------------------------------------------
  62. // Assert synchronously, deassert synchronously.
  63. // -----------------------------------------------
  64. always @(posedge clk) begin
  65. altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
  66. altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
  67. altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
  68. end
  69. assign reset_out = altera_reset_synchronizer_int_chain_out;
  70. end
  71. endgenerate
  72. endmodule