nios2_uc_mm_interconnect_0_router.sv 9.2 KB

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  1. // (C) 2001-2018 Intel Corporation. All rights reserved.
  2. // Your use of Intel Corporation's design tools, logic functions and other
  3. // software and tools, and its AMPP partner logic functions, and any output
  4. // files from any of the foregoing (including device programming or simulation
  5. // files), and any associated documentation or information are expressly subject
  6. // to the terms and conditions of the Intel Program License Subscription
  7. // Agreement, Intel FPGA IP License Agreement, or other applicable
  8. // license agreement, including, without limitation, that your use is for the
  9. // sole purpose of programming logic devices manufactured by Intel and sold by
  10. // Intel or its authorized distributors. Please refer to the applicable
  11. // agreement for further details.
  12. // Your use of Altera Corporation's design tools, logic functions and other
  13. // software and tools, and its AMPP partner logic functions, and any output
  14. // files any of the foregoing (including device programming or simulation
  15. // files), and any associated documentation or information are expressly subject
  16. // to the terms and conditions of the Altera Program License Subscription
  17. // Agreement, Altera MegaCore Function License Agreement, or other applicable
  18. // license agreement, including, without limitation, that your use is for the
  19. // sole purpose of programming logic devices manufactured by Altera and sold by
  20. // Altera or its authorized distributors. Please refer to the applicable
  21. // agreement for further details.
  22. // $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
  23. // $Revision: #1 $
  24. // $Date: 2018/07/18 $
  25. // $Author: psgswbuild $
  26. // -------------------------------------------------------
  27. // Merlin Router
  28. //
  29. // Asserts the appropriate one-hot encoded channel based on
  30. // either (a) the address or (b) the dest id. The DECODER_TYPE
  31. // parameter controls this behaviour. 0 means address decoder,
  32. // 1 means dest id decoder.
  33. //
  34. // In the case of (a), it also sets the destination id.
  35. // -------------------------------------------------------
  36. `timescale 1 ns / 1 ns
  37. module nios2_uc_mm_interconnect_0_router_default_decode
  38. #(
  39. parameter DEFAULT_CHANNEL = 3,
  40. DEFAULT_WR_CHANNEL = -1,
  41. DEFAULT_RD_CHANNEL = -1,
  42. DEFAULT_DESTID = 3
  43. )
  44. (output [82 - 80 : 0] default_destination_id,
  45. output [7-1 : 0] default_wr_channel,
  46. output [7-1 : 0] default_rd_channel,
  47. output [7-1 : 0] default_src_channel
  48. );
  49. assign default_destination_id =
  50. DEFAULT_DESTID[82 - 80 : 0];
  51. generate
  52. if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
  53. assign default_src_channel = '0;
  54. end
  55. else begin : default_channel_assignment
  56. assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
  57. end
  58. endgenerate
  59. generate
  60. if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
  61. assign default_wr_channel = '0;
  62. assign default_rd_channel = '0;
  63. end
  64. else begin : default_rw_channel_assignment
  65. assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
  66. assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
  67. end
  68. endgenerate
  69. endmodule
  70. module nios2_uc_mm_interconnect_0_router
  71. (
  72. // -------------------
  73. // Clock & Reset
  74. // -------------------
  75. input clk,
  76. input reset,
  77. // -------------------
  78. // Command Sink (Input)
  79. // -------------------
  80. input sink_valid,
  81. input [96-1 : 0] sink_data,
  82. input sink_startofpacket,
  83. input sink_endofpacket,
  84. output sink_ready,
  85. // -------------------
  86. // Command Source (Output)
  87. // -------------------
  88. output src_valid,
  89. output reg [96-1 : 0] src_data,
  90. output reg [7-1 : 0] src_channel,
  91. output src_startofpacket,
  92. output src_endofpacket,
  93. input src_ready
  94. );
  95. // -------------------------------------------------------
  96. // Local parameters and variables
  97. // -------------------------------------------------------
  98. localparam PKT_ADDR_H = 55;
  99. localparam PKT_ADDR_L = 36;
  100. localparam PKT_DEST_ID_H = 82;
  101. localparam PKT_DEST_ID_L = 80;
  102. localparam PKT_PROTECTION_H = 86;
  103. localparam PKT_PROTECTION_L = 84;
  104. localparam ST_DATA_W = 96;
  105. localparam ST_CHANNEL_W = 7;
  106. localparam DECODER_TYPE = 0;
  107. localparam PKT_TRANS_WRITE = 58;
  108. localparam PKT_TRANS_READ = 59;
  109. localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
  110. localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
  111. // -------------------------------------------------------
  112. // Figure out the number of bits to mask off for each slave span
  113. // during address decoding
  114. // -------------------------------------------------------
  115. localparam PAD0 = log2ceil(64'h80000 - 64'h40000);
  116. localparam PAD1 = log2ceil(64'h81000 - 64'h80800);
  117. localparam PAD2 = log2ceil(64'h81050 - 64'h81040);
  118. localparam PAD3 = log2ceil(64'h81060 - 64'h81050);
  119. localparam PAD4 = log2ceil(64'h81070 - 64'h81060);
  120. localparam PAD5 = log2ceil(64'h81080 - 64'h81070);
  121. localparam PAD6 = log2ceil(64'h81090 - 64'h81088);
  122. // -------------------------------------------------------
  123. // Work out which address bits are significant based on the
  124. // address range of the slaves. If the required width is too
  125. // large or too small, we use the address field width instead.
  126. // -------------------------------------------------------
  127. localparam ADDR_RANGE = 64'h81090;
  128. localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
  129. localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
  130. (RANGE_ADDR_WIDTH == 0) ?
  131. PKT_ADDR_H :
  132. PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
  133. localparam RG = RANGE_ADDR_WIDTH-1;
  134. localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
  135. reg [PKT_ADDR_W-1 : 0] address;
  136. always @* begin
  137. address = {PKT_ADDR_W{1'b0}};
  138. address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
  139. end
  140. // -------------------------------------------------------
  141. // Pass almost everything through, untouched
  142. // -------------------------------------------------------
  143. assign sink_ready = src_ready;
  144. assign src_valid = sink_valid;
  145. assign src_startofpacket = sink_startofpacket;
  146. assign src_endofpacket = sink_endofpacket;
  147. wire [PKT_DEST_ID_W-1:0] default_destid;
  148. wire [7-1 : 0] default_src_channel;
  149. // -------------------------------------------------------
  150. // Write and read transaction signals
  151. // -------------------------------------------------------
  152. wire read_transaction;
  153. assign read_transaction = sink_data[PKT_TRANS_READ];
  154. nios2_uc_mm_interconnect_0_router_default_decode the_default_decode(
  155. .default_destination_id (default_destid),
  156. .default_wr_channel (),
  157. .default_rd_channel (),
  158. .default_src_channel (default_src_channel)
  159. );
  160. always @* begin
  161. src_data = sink_data;
  162. src_channel = default_src_channel;
  163. src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
  164. // --------------------------------------------------
  165. // Address Decoder
  166. // Sets the channel and destination ID based on the address
  167. // --------------------------------------------------
  168. // ( 0x40000 .. 0x80000 )
  169. if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h40000 ) begin
  170. src_channel = 7'b0001000;
  171. src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
  172. end
  173. // ( 0x80800 .. 0x81000 )
  174. if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h80800 ) begin
  175. src_channel = 7'b0000100;
  176. src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
  177. end
  178. // ( 0x81040 .. 0x81050 )
  179. if ( {address[RG:PAD2],{PAD2{1'b0}}} == 20'h81040 && read_transaction ) begin
  180. src_channel = 7'b1000000;
  181. src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
  182. end
  183. // ( 0x81050 .. 0x81060 )
  184. if ( {address[RG:PAD3],{PAD3{1'b0}}} == 20'h81050 ) begin
  185. src_channel = 7'b0100000;
  186. src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
  187. end
  188. // ( 0x81060 .. 0x81070 )
  189. if ( {address[RG:PAD4],{PAD4{1'b0}}} == 20'h81060 ) begin
  190. src_channel = 7'b0010000;
  191. src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
  192. end
  193. // ( 0x81070 .. 0x81080 )
  194. if ( {address[RG:PAD5],{PAD5{1'b0}}} == 20'h81070 ) begin
  195. src_channel = 7'b0000010;
  196. src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
  197. end
  198. // ( 0x81088 .. 0x81090 )
  199. if ( {address[RG:PAD6],{PAD6{1'b0}}} == 20'h81088 ) begin
  200. src_channel = 7'b0000001;
  201. src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
  202. end
  203. end
  204. // --------------------------------------------------
  205. // Ceil(log2()) function
  206. // --------------------------------------------------
  207. function integer log2ceil;
  208. input reg[65:0] val;
  209. reg [65:0] i;
  210. begin
  211. i = 1;
  212. log2ceil = 0;
  213. while (i < val) begin
  214. log2ceil = log2ceil + 1;
  215. i = i << 1;
  216. end
  217. end
  218. endfunction
  219. endmodule