nios2_uc_irq_mapper.sv 1.6 KB

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  1. // (C) 2001-2018 Intel Corporation. All rights reserved.
  2. // Your use of Intel Corporation's design tools, logic functions and other
  3. // software and tools, and its AMPP partner logic functions, and any output
  4. // files from any of the foregoing (including device programming or simulation
  5. // files), and any associated documentation or information are expressly subject
  6. // to the terms and conditions of the Intel Program License Subscription
  7. // Agreement, Intel FPGA IP License Agreement, or other applicable
  8. // license agreement, including, without limitation, that your use is for the
  9. // sole purpose of programming logic devices manufactured by Intel and sold by
  10. // Intel or its authorized distributors. Please refer to the applicable
  11. // agreement for further details.
  12. // $Id: //acds/rel/18.1std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
  13. // $Revision: #1 $
  14. // $Date: 2018/07/18 $
  15. // $Author: psgswbuild $
  16. // -------------------------------------------------------
  17. // Altera IRQ Mapper
  18. //
  19. // Parameters
  20. // NUM_RCVRS : 1
  21. // SENDER_IRW_WIDTH : 32
  22. // IRQ_MAP : 0:0
  23. //
  24. // -------------------------------------------------------
  25. `timescale 1 ns / 1 ns
  26. module nios2_uc_irq_mapper
  27. (
  28. // -------------------
  29. // Clock & Reset
  30. // -------------------
  31. input clk,
  32. input reset,
  33. // -------------------
  34. // IRQ Receivers
  35. // -------------------
  36. input receiver0_irq,
  37. // -------------------
  38. // Command Source (Output)
  39. // -------------------
  40. output reg [31 : 0] sender_irq
  41. );
  42. always @* begin
  43. sender_irq = 0;
  44. sender_irq[0] = receiver0_irq;
  45. end
  46. endmodule