myfirst_niosii.qsf 6.4 KB

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  1. # -------------------------------------------------------------------------- #
  2. #
  3. # Copyright (C) 2019 Intel Corporation. All rights reserved.
  4. # Your use of Intel Corporation's design tools, logic functions
  5. # and other software and tools, and any partner logic
  6. # functions, and any output files from any of the foregoing
  7. # (including device programming or simulation files), and any
  8. # associated documentation or information are expressly subject
  9. # to the terms and conditions of the Intel Program License
  10. # Subscription Agreement, the Intel Quartus Prime License Agreement,
  11. # the Intel FPGA IP License Agreement, or other applicable license
  12. # agreement, including, without limitation, that your use is for
  13. # the sole purpose of programming logic devices manufactured by
  14. # Intel and sold by Intel or its authorized distributors. Please
  15. # refer to the applicable agreement for further details, at
  16. # https://fpgasoftware.intel.com/eula.
  17. #
  18. # -------------------------------------------------------------------------- #
  19. #
  20. # Quartus Prime
  21. # Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
  22. # Date created = 15:57:19 November 19, 2020
  23. #
  24. # -------------------------------------------------------------------------- #
  25. #
  26. # Notes:
  27. #
  28. # 1) The default values for assignments are stored in the file:
  29. # myfirst_niosii_assignment_defaults.qdf
  30. # If this file doesn't exist, see file:
  31. # assignment_defaults.qdf
  32. #
  33. # 2) Altera recommends that you do not modify this file. This
  34. # file is updated automatically by the Quartus Prime software
  35. # and any changes you make may be lost or overwritten.
  36. #
  37. # -------------------------------------------------------------------------- #
  38. set_global_assignment -name FAMILY "Cyclone IV E"
  39. set_global_assignment -name DEVICE EP4CE115F29C7
  40. set_global_assignment -name TOP_LEVEL_ENTITY myfirst_niosii
  41. set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1
  42. set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:57:19 NOVEMBER 19, 2020"
  43. set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
  44. set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
  45. set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
  46. set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
  47. set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
  48. set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
  49. set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
  50. set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
  51. set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
  52. set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
  53. set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
  54. set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
  55. set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
  56. set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
  57. set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
  58. set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Blast FPGA" -entity nios2_uc.qip
  59. set_global_assignment -name EDA_INPUT_GND_NAME GND -entity nios2_uc.qip -section_id eda_design_synthesis
  60. set_global_assignment -name EDA_INPUT_VCC_NAME VDD -entity nios2_uc.qip -section_id eda_design_synthesis
  61. set_global_assignment -name EDA_LMF_FILE blast.lmf -entity nios2_uc.qip -section_id eda_design_synthesis
  62. set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES OFF -entity nios2_uc.qip -section_id eda_design_synthesis
  63. set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -entity nios2_uc.qip -section_id eda_design_synthesis
  64. set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -entity nios2_uc.qip -section_id eda_design_synthesis
  65. set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
  66. set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
  67. set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
  68. set_global_assignment -name QIP_FILE nios2_uc/synthesis/nios2_uc.qip
  69. set_global_assignment -name VHDL_FILE myfirst_niosii.vhd
  70. set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Blast FPGA" -entity myfirst_niosii.vhd
  71. set_global_assignment -name EDA_INPUT_GND_NAME GND -entity myfirst_niosii.vhd -section_id eda_design_synthesis
  72. set_global_assignment -name EDA_INPUT_VCC_NAME VDD -entity myfirst_niosii.vhd -section_id eda_design_synthesis
  73. set_global_assignment -name EDA_LMF_FILE blast.lmf -entity myfirst_niosii.vhd -section_id eda_design_synthesis
  74. set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES OFF -entity myfirst_niosii.vhd -section_id eda_design_synthesis
  75. set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -entity myfirst_niosii.vhd -section_id eda_design_synthesis
  76. set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -entity myfirst_niosii.vhd -section_id eda_design_synthesis
  77. set_location_assignment PIN_E21 -to pio_led[0]
  78. set_location_assignment PIN_E22 -to pio_led[1]
  79. set_location_assignment PIN_E25 -to pio_led[2]
  80. set_location_assignment PIN_E24 -to pio_led[3]
  81. set_location_assignment PIN_H21 -to pio_led[4]
  82. set_location_assignment PIN_G20 -to pio_led[5]
  83. set_location_assignment PIN_G22 -to pio_led[6]
  84. set_location_assignment PIN_G21 -to pio_led[7]
  85. set_location_assignment PIN_G19 -to pio_led[8]
  86. set_location_assignment PIN_Y23 -to rst
  87. set_location_assignment PIN_Y2 -to clk
  88. set_location_assignment PIN_F19 -to pio_led[9]
  89. set_location_assignment PIN_E19 -to pio_led[10]
  90. set_location_assignment PIN_F21 -to pio_led[11]
  91. set_location_assignment PIN_F18 -to pio_led[12]
  92. set_location_assignment PIN_E18 -to pio_led[13]
  93. set_location_assignment PIN_J19 -to pio_led[14]
  94. set_location_assignment PIN_H19 -to pio_led[15]
  95. set_location_assignment PIN_J17 -to pio_led[16]
  96. set_location_assignment PIN_G17 -to pio_led[17]
  97. set_location_assignment PIN_J15 -to pio_led[18]
  98. set_location_assignment PIN_H16 -to pio_led[19]
  99. set_location_assignment PIN_J16 -to pio_led[20]
  100. set_location_assignment PIN_H17 -to pio_led[21]
  101. set_location_assignment PIN_F15 -to pio_led[22]
  102. set_location_assignment PIN_G15 -to pio_led[23]
  103. set_location_assignment PIN_G16 -to pio_led[24]
  104. set_location_assignment PIN_H15 -to pio_led[25]
  105. set_location_assignment PIN_M23 -to toggle_button
  106. set_location_assignment PIN_F17 -to toggle_led
  107. set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top