# -------------------------------------------------------------------------- # # # Copyright (C) 2019 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details, at # https://fpgasoftware.intel.com/eula. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition # Date created = 15:57:19 November 19, 2020 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # myfirst_niosii_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE115F29C7 set_global_assignment -name TOP_LEVEL_ENTITY myfirst_niosii set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:57:19 NOVEMBER 19, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Blast FPGA" -entity nios2_uc.qip set_global_assignment -name EDA_INPUT_GND_NAME GND -entity nios2_uc.qip -section_id eda_design_synthesis set_global_assignment -name EDA_INPUT_VCC_NAME VDD -entity nios2_uc.qip -section_id eda_design_synthesis set_global_assignment -name EDA_LMF_FILE blast.lmf -entity nios2_uc.qip -section_id eda_design_synthesis set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES OFF -entity nios2_uc.qip -section_id eda_design_synthesis set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -entity nios2_uc.qip -section_id eda_design_synthesis set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -entity nios2_uc.qip -section_id eda_design_synthesis set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name QIP_FILE nios2_uc/synthesis/nios2_uc.qip set_global_assignment -name VHDL_FILE myfirst_niosii.vhd set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Blast FPGA" -entity myfirst_niosii.vhd set_global_assignment -name EDA_INPUT_GND_NAME GND -entity myfirst_niosii.vhd -section_id eda_design_synthesis set_global_assignment -name EDA_INPUT_VCC_NAME VDD -entity myfirst_niosii.vhd -section_id eda_design_synthesis set_global_assignment -name EDA_LMF_FILE blast.lmf -entity myfirst_niosii.vhd -section_id eda_design_synthesis set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES OFF -entity myfirst_niosii.vhd -section_id eda_design_synthesis set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -entity myfirst_niosii.vhd -section_id eda_design_synthesis set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -entity myfirst_niosii.vhd -section_id eda_design_synthesis set_location_assignment PIN_E21 -to pio_led[0] set_location_assignment PIN_E22 -to pio_led[1] set_location_assignment PIN_E25 -to pio_led[2] set_location_assignment PIN_E24 -to pio_led[3] set_location_assignment PIN_H21 -to pio_led[4] set_location_assignment PIN_G20 -to pio_led[5] set_location_assignment PIN_G22 -to pio_led[6] set_location_assignment PIN_G21 -to pio_led[7] set_location_assignment PIN_G19 -to pio_led[8] set_location_assignment PIN_Y23 -to rst set_location_assignment PIN_Y2 -to clk set_location_assignment PIN_F19 -to pio_led[9] set_location_assignment PIN_E19 -to pio_led[10] set_location_assignment PIN_F21 -to pio_led[11] set_location_assignment PIN_F18 -to pio_led[12] set_location_assignment PIN_E18 -to pio_led[13] set_location_assignment PIN_J19 -to pio_led[14] set_location_assignment PIN_H19 -to pio_led[15] set_location_assignment PIN_J17 -to pio_led[16] set_location_assignment PIN_G17 -to pio_led[17] set_location_assignment PIN_J15 -to pio_led[18] set_location_assignment PIN_H16 -to pio_led[19] set_location_assignment PIN_J16 -to pio_led[20] set_location_assignment PIN_H17 -to pio_led[21] set_location_assignment PIN_F15 -to pio_led[22] set_location_assignment PIN_G15 -to pio_led[23] set_location_assignment PIN_G16 -to pio_led[24] set_location_assignment PIN_H15 -to pio_led[25] set_location_assignment PIN_M23 -to toggle_button set_location_assignment PIN_F17 -to toggle_led set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top