nios2_uc_nios2_cpu_test_bench.v 27 KB

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  1. //Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
  2. //use of Altera Corporation's design tools, logic functions and other
  3. //software and tools, and its AMPP partner logic functions, and any
  4. //output files any of the foregoing (including device programming or
  5. //simulation files), and any associated documentation or information are
  6. //expressly subject to the terms and conditions of the Altera Program
  7. //License Subscription Agreement or other applicable license agreement,
  8. //including, without limitation, that your use is for the sole purpose
  9. //of programming logic devices manufactured by Altera and sold by Altera
  10. //or its authorized distributors. Please refer to the applicable
  11. //agreement for further details.
  12. // synthesis translate_off
  13. `timescale 1ns / 1ps
  14. // synthesis translate_on
  15. // turn off superfluous verilog processor warnings
  16. // altera message_level Level1
  17. // altera message_off 10034 10035 10036 10037 10230 10240 10030
  18. module nios2_uc_nios2_cpu_test_bench (
  19. // inputs:
  20. D_iw,
  21. D_iw_op,
  22. D_iw_opx,
  23. D_valid,
  24. E_valid,
  25. F_pcb,
  26. F_valid,
  27. R_ctrl_ld,
  28. R_ctrl_ld_non_io,
  29. R_dst_regnum,
  30. R_wr_dst_reg,
  31. W_valid,
  32. W_vinst,
  33. W_wr_data,
  34. av_ld_data_aligned_unfiltered,
  35. clk,
  36. d_address,
  37. d_byteenable,
  38. d_read,
  39. d_write,
  40. i_address,
  41. i_read,
  42. i_readdata,
  43. i_waitrequest,
  44. reset_n,
  45. // outputs:
  46. av_ld_data_aligned_filtered,
  47. test_has_ended
  48. )
  49. ;
  50. output [ 31: 0] av_ld_data_aligned_filtered;
  51. output test_has_ended;
  52. input [ 31: 0] D_iw;
  53. input [ 5: 0] D_iw_op;
  54. input [ 5: 0] D_iw_opx;
  55. input D_valid;
  56. input E_valid;
  57. input [ 19: 0] F_pcb;
  58. input F_valid;
  59. input R_ctrl_ld;
  60. input R_ctrl_ld_non_io;
  61. input [ 4: 0] R_dst_regnum;
  62. input R_wr_dst_reg;
  63. input W_valid;
  64. input [271: 0] W_vinst;
  65. input [ 31: 0] W_wr_data;
  66. input [ 31: 0] av_ld_data_aligned_unfiltered;
  67. input clk;
  68. input [ 19: 0] d_address;
  69. input [ 3: 0] d_byteenable;
  70. input d_read;
  71. input d_write;
  72. input [ 19: 0] i_address;
  73. input i_read;
  74. input [ 31: 0] i_readdata;
  75. input i_waitrequest;
  76. input reset_n;
  77. wire D_is_opx_inst;
  78. wire D_op_add;
  79. wire D_op_addi;
  80. wire D_op_and;
  81. wire D_op_andhi;
  82. wire D_op_andi;
  83. wire D_op_beq;
  84. wire D_op_bge;
  85. wire D_op_bgeu;
  86. wire D_op_blt;
  87. wire D_op_bltu;
  88. wire D_op_bne;
  89. wire D_op_br;
  90. wire D_op_break;
  91. wire D_op_bret;
  92. wire D_op_call;
  93. wire D_op_callr;
  94. wire D_op_cmpeq;
  95. wire D_op_cmpeqi;
  96. wire D_op_cmpge;
  97. wire D_op_cmpgei;
  98. wire D_op_cmpgeu;
  99. wire D_op_cmpgeui;
  100. wire D_op_cmplt;
  101. wire D_op_cmplti;
  102. wire D_op_cmpltu;
  103. wire D_op_cmpltui;
  104. wire D_op_cmpne;
  105. wire D_op_cmpnei;
  106. wire D_op_crst;
  107. wire D_op_custom;
  108. wire D_op_div;
  109. wire D_op_divu;
  110. wire D_op_eret;
  111. wire D_op_flushd;
  112. wire D_op_flushda;
  113. wire D_op_flushi;
  114. wire D_op_flushp;
  115. wire D_op_hbreak;
  116. wire D_op_initd;
  117. wire D_op_initda;
  118. wire D_op_initi;
  119. wire D_op_intr;
  120. wire D_op_jmp;
  121. wire D_op_jmpi;
  122. wire D_op_ldb;
  123. wire D_op_ldbio;
  124. wire D_op_ldbu;
  125. wire D_op_ldbuio;
  126. wire D_op_ldh;
  127. wire D_op_ldhio;
  128. wire D_op_ldhu;
  129. wire D_op_ldhuio;
  130. wire D_op_ldl;
  131. wire D_op_ldw;
  132. wire D_op_ldwio;
  133. wire D_op_mul;
  134. wire D_op_muli;
  135. wire D_op_mulxss;
  136. wire D_op_mulxsu;
  137. wire D_op_mulxuu;
  138. wire D_op_nextpc;
  139. wire D_op_nios_custom_instr_floating_point_0;
  140. wire D_op_nor;
  141. wire D_op_op_rsv02;
  142. wire D_op_op_rsv09;
  143. wire D_op_op_rsv10;
  144. wire D_op_op_rsv17;
  145. wire D_op_op_rsv18;
  146. wire D_op_op_rsv25;
  147. wire D_op_op_rsv26;
  148. wire D_op_op_rsv33;
  149. wire D_op_op_rsv34;
  150. wire D_op_op_rsv41;
  151. wire D_op_op_rsv42;
  152. wire D_op_op_rsv49;
  153. wire D_op_op_rsv57;
  154. wire D_op_op_rsv61;
  155. wire D_op_op_rsv62;
  156. wire D_op_op_rsv63;
  157. wire D_op_opx_rsv00;
  158. wire D_op_opx_rsv10;
  159. wire D_op_opx_rsv15;
  160. wire D_op_opx_rsv17;
  161. wire D_op_opx_rsv21;
  162. wire D_op_opx_rsv25;
  163. wire D_op_opx_rsv33;
  164. wire D_op_opx_rsv34;
  165. wire D_op_opx_rsv35;
  166. wire D_op_opx_rsv42;
  167. wire D_op_opx_rsv43;
  168. wire D_op_opx_rsv44;
  169. wire D_op_opx_rsv47;
  170. wire D_op_opx_rsv50;
  171. wire D_op_opx_rsv51;
  172. wire D_op_opx_rsv55;
  173. wire D_op_opx_rsv56;
  174. wire D_op_opx_rsv60;
  175. wire D_op_opx_rsv63;
  176. wire D_op_or;
  177. wire D_op_orhi;
  178. wire D_op_ori;
  179. wire D_op_rdctl;
  180. wire D_op_rdprs;
  181. wire D_op_ret;
  182. wire D_op_rol;
  183. wire D_op_roli;
  184. wire D_op_ror;
  185. wire D_op_sll;
  186. wire D_op_slli;
  187. wire D_op_sra;
  188. wire D_op_srai;
  189. wire D_op_srl;
  190. wire D_op_srli;
  191. wire D_op_stb;
  192. wire D_op_stbio;
  193. wire D_op_stc;
  194. wire D_op_sth;
  195. wire D_op_sthio;
  196. wire D_op_stw;
  197. wire D_op_stwio;
  198. wire D_op_sub;
  199. wire D_op_sync;
  200. wire D_op_trap;
  201. wire D_op_wrctl;
  202. wire D_op_wrprs;
  203. wire D_op_xor;
  204. wire D_op_xorhi;
  205. wire D_op_xori;
  206. wire [ 31: 0] av_ld_data_aligned_filtered;
  207. wire av_ld_data_aligned_unfiltered_0_is_x;
  208. wire av_ld_data_aligned_unfiltered_10_is_x;
  209. wire av_ld_data_aligned_unfiltered_11_is_x;
  210. wire av_ld_data_aligned_unfiltered_12_is_x;
  211. wire av_ld_data_aligned_unfiltered_13_is_x;
  212. wire av_ld_data_aligned_unfiltered_14_is_x;
  213. wire av_ld_data_aligned_unfiltered_15_is_x;
  214. wire av_ld_data_aligned_unfiltered_16_is_x;
  215. wire av_ld_data_aligned_unfiltered_17_is_x;
  216. wire av_ld_data_aligned_unfiltered_18_is_x;
  217. wire av_ld_data_aligned_unfiltered_19_is_x;
  218. wire av_ld_data_aligned_unfiltered_1_is_x;
  219. wire av_ld_data_aligned_unfiltered_20_is_x;
  220. wire av_ld_data_aligned_unfiltered_21_is_x;
  221. wire av_ld_data_aligned_unfiltered_22_is_x;
  222. wire av_ld_data_aligned_unfiltered_23_is_x;
  223. wire av_ld_data_aligned_unfiltered_24_is_x;
  224. wire av_ld_data_aligned_unfiltered_25_is_x;
  225. wire av_ld_data_aligned_unfiltered_26_is_x;
  226. wire av_ld_data_aligned_unfiltered_27_is_x;
  227. wire av_ld_data_aligned_unfiltered_28_is_x;
  228. wire av_ld_data_aligned_unfiltered_29_is_x;
  229. wire av_ld_data_aligned_unfiltered_2_is_x;
  230. wire av_ld_data_aligned_unfiltered_30_is_x;
  231. wire av_ld_data_aligned_unfiltered_31_is_x;
  232. wire av_ld_data_aligned_unfiltered_3_is_x;
  233. wire av_ld_data_aligned_unfiltered_4_is_x;
  234. wire av_ld_data_aligned_unfiltered_5_is_x;
  235. wire av_ld_data_aligned_unfiltered_6_is_x;
  236. wire av_ld_data_aligned_unfiltered_7_is_x;
  237. wire av_ld_data_aligned_unfiltered_8_is_x;
  238. wire av_ld_data_aligned_unfiltered_9_is_x;
  239. wire test_has_ended;
  240. assign D_op_call = D_iw_op == 0;
  241. assign D_op_jmpi = D_iw_op == 1;
  242. assign D_op_op_rsv02 = D_iw_op == 2;
  243. assign D_op_ldbu = D_iw_op == 3;
  244. assign D_op_addi = D_iw_op == 4;
  245. assign D_op_stb = D_iw_op == 5;
  246. assign D_op_br = D_iw_op == 6;
  247. assign D_op_ldb = D_iw_op == 7;
  248. assign D_op_cmpgei = D_iw_op == 8;
  249. assign D_op_op_rsv09 = D_iw_op == 9;
  250. assign D_op_op_rsv10 = D_iw_op == 10;
  251. assign D_op_ldhu = D_iw_op == 11;
  252. assign D_op_andi = D_iw_op == 12;
  253. assign D_op_sth = D_iw_op == 13;
  254. assign D_op_bge = D_iw_op == 14;
  255. assign D_op_ldh = D_iw_op == 15;
  256. assign D_op_cmplti = D_iw_op == 16;
  257. assign D_op_op_rsv17 = D_iw_op == 17;
  258. assign D_op_op_rsv18 = D_iw_op == 18;
  259. assign D_op_initda = D_iw_op == 19;
  260. assign D_op_ori = D_iw_op == 20;
  261. assign D_op_stw = D_iw_op == 21;
  262. assign D_op_blt = D_iw_op == 22;
  263. assign D_op_ldw = D_iw_op == 23;
  264. assign D_op_cmpnei = D_iw_op == 24;
  265. assign D_op_op_rsv25 = D_iw_op == 25;
  266. assign D_op_op_rsv26 = D_iw_op == 26;
  267. assign D_op_flushda = D_iw_op == 27;
  268. assign D_op_xori = D_iw_op == 28;
  269. assign D_op_stc = D_iw_op == 29;
  270. assign D_op_bne = D_iw_op == 30;
  271. assign D_op_ldl = D_iw_op == 31;
  272. assign D_op_cmpeqi = D_iw_op == 32;
  273. assign D_op_op_rsv33 = D_iw_op == 33;
  274. assign D_op_op_rsv34 = D_iw_op == 34;
  275. assign D_op_ldbuio = D_iw_op == 35;
  276. assign D_op_muli = D_iw_op == 36;
  277. assign D_op_stbio = D_iw_op == 37;
  278. assign D_op_beq = D_iw_op == 38;
  279. assign D_op_ldbio = D_iw_op == 39;
  280. assign D_op_cmpgeui = D_iw_op == 40;
  281. assign D_op_op_rsv41 = D_iw_op == 41;
  282. assign D_op_op_rsv42 = D_iw_op == 42;
  283. assign D_op_ldhuio = D_iw_op == 43;
  284. assign D_op_andhi = D_iw_op == 44;
  285. assign D_op_sthio = D_iw_op == 45;
  286. assign D_op_bgeu = D_iw_op == 46;
  287. assign D_op_ldhio = D_iw_op == 47;
  288. assign D_op_cmpltui = D_iw_op == 48;
  289. assign D_op_op_rsv49 = D_iw_op == 49;
  290. assign D_op_custom = D_iw_op == 50;
  291. assign D_op_initd = D_iw_op == 51;
  292. assign D_op_orhi = D_iw_op == 52;
  293. assign D_op_stwio = D_iw_op == 53;
  294. assign D_op_bltu = D_iw_op == 54;
  295. assign D_op_ldwio = D_iw_op == 55;
  296. assign D_op_rdprs = D_iw_op == 56;
  297. assign D_op_op_rsv57 = D_iw_op == 57;
  298. assign D_op_flushd = D_iw_op == 59;
  299. assign D_op_xorhi = D_iw_op == 60;
  300. assign D_op_op_rsv61 = D_iw_op == 61;
  301. assign D_op_op_rsv62 = D_iw_op == 62;
  302. assign D_op_op_rsv63 = D_iw_op == 63;
  303. assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
  304. assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
  305. assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
  306. assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
  307. assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
  308. assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
  309. assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
  310. assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
  311. assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
  312. assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
  313. assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
  314. assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
  315. assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
  316. assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
  317. assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
  318. assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
  319. assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
  320. assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
  321. assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
  322. assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
  323. assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
  324. assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
  325. assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
  326. assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
  327. assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
  328. assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
  329. assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
  330. assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
  331. assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
  332. assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
  333. assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
  334. assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
  335. assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
  336. assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
  337. assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
  338. assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
  339. assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
  340. assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
  341. assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
  342. assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
  343. assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
  344. assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
  345. assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
  346. assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
  347. assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
  348. assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
  349. assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
  350. assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
  351. assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
  352. assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
  353. assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
  354. assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
  355. assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
  356. assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
  357. assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
  358. assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
  359. assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
  360. assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
  361. assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
  362. assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
  363. assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
  364. assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
  365. assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
  366. assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
  367. assign D_op_nios_custom_instr_floating_point_0 = D_op_custom & 1'b1;
  368. assign D_is_opx_inst = D_iw_op == 58;
  369. assign test_has_ended = 1'b0;
  370. //synthesis translate_off
  371. //////////////// SIMULATION-ONLY CONTENTS
  372. //Clearing 'X' data bits
  373. assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
  374. assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
  375. assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
  376. assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
  377. assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
  378. assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
  379. assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
  380. assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
  381. assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
  382. assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
  383. assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
  384. assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
  385. assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
  386. assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
  387. assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
  388. assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
  389. assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
  390. assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
  391. assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
  392. assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
  393. assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
  394. assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
  395. assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
  396. assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
  397. assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
  398. assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
  399. assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
  400. assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
  401. assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
  402. assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
  403. assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
  404. assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
  405. assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
  406. assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
  407. assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
  408. assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
  409. assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
  410. assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
  411. assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
  412. assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
  413. assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
  414. assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
  415. assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
  416. assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
  417. assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
  418. assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
  419. assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
  420. assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
  421. assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
  422. assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
  423. assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
  424. assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
  425. assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
  426. assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
  427. assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
  428. assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
  429. assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
  430. assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
  431. assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
  432. assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
  433. assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
  434. assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
  435. assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
  436. assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
  437. always @(posedge clk)
  438. begin
  439. if (reset_n)
  440. if (^(F_valid) === 1'bx)
  441. begin
  442. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/F_valid is 'x'\n", $time);
  443. $stop;
  444. end
  445. end
  446. always @(posedge clk)
  447. begin
  448. if (reset_n)
  449. if (^(D_valid) === 1'bx)
  450. begin
  451. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/D_valid is 'x'\n", $time);
  452. $stop;
  453. end
  454. end
  455. always @(posedge clk)
  456. begin
  457. if (reset_n)
  458. if (^(E_valid) === 1'bx)
  459. begin
  460. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/E_valid is 'x'\n", $time);
  461. $stop;
  462. end
  463. end
  464. always @(posedge clk)
  465. begin
  466. if (reset_n)
  467. if (^(W_valid) === 1'bx)
  468. begin
  469. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/W_valid is 'x'\n", $time);
  470. $stop;
  471. end
  472. end
  473. always @(posedge clk or negedge reset_n)
  474. begin
  475. if (reset_n == 0)
  476. begin
  477. end
  478. else if (W_valid)
  479. if (^(R_wr_dst_reg) === 1'bx)
  480. begin
  481. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
  482. $stop;
  483. end
  484. end
  485. always @(posedge clk or negedge reset_n)
  486. begin
  487. if (reset_n == 0)
  488. begin
  489. end
  490. else if (W_valid & R_wr_dst_reg)
  491. if (^(W_wr_data) === 1'bx)
  492. begin
  493. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/W_wr_data is 'x'\n", $time);
  494. $stop;
  495. end
  496. end
  497. always @(posedge clk or negedge reset_n)
  498. begin
  499. if (reset_n == 0)
  500. begin
  501. end
  502. else if (W_valid & R_wr_dst_reg)
  503. if (^(R_dst_regnum) === 1'bx)
  504. begin
  505. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
  506. $stop;
  507. end
  508. end
  509. always @(posedge clk)
  510. begin
  511. if (reset_n)
  512. if (^(d_write) === 1'bx)
  513. begin
  514. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/d_write is 'x'\n", $time);
  515. $stop;
  516. end
  517. end
  518. always @(posedge clk or negedge reset_n)
  519. begin
  520. if (reset_n == 0)
  521. begin
  522. end
  523. else if (d_write)
  524. if (^(d_byteenable) === 1'bx)
  525. begin
  526. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/d_byteenable is 'x'\n", $time);
  527. $stop;
  528. end
  529. end
  530. always @(posedge clk or negedge reset_n)
  531. begin
  532. if (reset_n == 0)
  533. begin
  534. end
  535. else if (d_write | d_read)
  536. if (^(d_address) === 1'bx)
  537. begin
  538. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/d_address is 'x'\n", $time);
  539. $stop;
  540. end
  541. end
  542. always @(posedge clk)
  543. begin
  544. if (reset_n)
  545. if (^(d_read) === 1'bx)
  546. begin
  547. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/d_read is 'x'\n", $time);
  548. $stop;
  549. end
  550. end
  551. always @(posedge clk)
  552. begin
  553. if (reset_n)
  554. if (^(i_read) === 1'bx)
  555. begin
  556. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/i_read is 'x'\n", $time);
  557. $stop;
  558. end
  559. end
  560. always @(posedge clk or negedge reset_n)
  561. begin
  562. if (reset_n == 0)
  563. begin
  564. end
  565. else if (i_read)
  566. if (^(i_address) === 1'bx)
  567. begin
  568. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/i_address is 'x'\n", $time);
  569. $stop;
  570. end
  571. end
  572. always @(posedge clk or negedge reset_n)
  573. begin
  574. if (reset_n == 0)
  575. begin
  576. end
  577. else if (i_read & ~i_waitrequest)
  578. if (^(i_readdata) === 1'bx)
  579. begin
  580. $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/i_readdata is 'x'\n", $time);
  581. $stop;
  582. end
  583. end
  584. always @(posedge clk or negedge reset_n)
  585. begin
  586. if (reset_n == 0)
  587. begin
  588. end
  589. else if (W_valid & R_ctrl_ld)
  590. if (^(av_ld_data_aligned_unfiltered) === 1'bx)
  591. begin
  592. $write("%0d ns: WARNING: nios2_uc_nios2_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
  593. end
  594. end
  595. always @(posedge clk or negedge reset_n)
  596. begin
  597. if (reset_n == 0)
  598. begin
  599. end
  600. else if (W_valid & R_wr_dst_reg)
  601. if (^(W_wr_data) === 1'bx)
  602. begin
  603. $write("%0d ns: WARNING: nios2_uc_nios2_cpu_test_bench/W_wr_data is 'x'\n", $time);
  604. end
  605. end
  606. //////////////// END SIMULATION-ONLY CONTENTS
  607. //synthesis translate_on
  608. //synthesis read_comments_as_HDL on
  609. //
  610. // assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
  611. //
  612. //synthesis read_comments_as_HDL off
  613. endmodule