nios2_uc_pio_LED.v 2.1 KB

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  12. // synthesis translate_off
  13. `timescale 1ns / 1ps
  14. // synthesis translate_on
  15. // turn off superfluous verilog processor warnings
  16. // altera message_level Level1
  17. // altera message_off 10034 10035 10036 10037 10230 10240 10030
  18. module nios2_uc_pio_LED (
  19. // inputs:
  20. address,
  21. chipselect,
  22. clk,
  23. reset_n,
  24. write_n,
  25. writedata,
  26. // outputs:
  27. out_port,
  28. readdata
  29. )
  30. ;
  31. output [ 31: 0] out_port;
  32. output [ 31: 0] readdata;
  33. input [ 1: 0] address;
  34. input chipselect;
  35. input clk;
  36. input reset_n;
  37. input write_n;
  38. input [ 31: 0] writedata;
  39. wire clk_en;
  40. reg [ 31: 0] data_out;
  41. wire [ 31: 0] out_port;
  42. wire [ 31: 0] read_mux_out;
  43. wire [ 31: 0] readdata;
  44. assign clk_en = 1;
  45. //s1, which is an e_avalon_slave
  46. assign read_mux_out = {32 {(address == 0)}} & data_out;
  47. always @(posedge clk or negedge reset_n)
  48. begin
  49. if (reset_n == 0)
  50. data_out <= 0;
  51. else if (chipselect && ~write_n && (address == 0))
  52. data_out <= writedata[31 : 0];
  53. end
  54. assign readdata = {32'b0 | read_mux_out};
  55. assign out_port = data_out;
  56. endmodule