DE2-115-FPGA-Pong/README.md

DE2-115-FPGA-Pong

This is a Pong game on an Altera FPGA as an exercise in Hardware-/Software-Codesign.

The video below shows it in action, running on an university-made extension board.

Source files

.
├── myfirst_niosii.vhd
├── nios2_uc
│   ├── nios2_uc.bsf
│   └── synthesis
│       └── nios2_uc.vhd
├── README.md
└── software
    ├── hello_world
    ├── hello_world_bsp
    ├── Pong_Code
    │   ├── Display.h
    │   ├── Main.c
    │   └── structs.h
    └── Pong_Code_bsp

Data flow

This diagram shows all the implemented parts and the singnals to connect them. The implementation is split in pysical Hareware, programmable logic as VHDL and instruction based C software.

Flowcharts of the VHDL program

Below are shown the two main processes that are implemented in VHDL. They run simultanously and independent of each other. All processes and the synthesized CPU are connected to a common 50 MHz clock and a reset signal. When reset, all processes are asynchronously forced to output their default values, as seen in the first block.

Multiplex process

Debounce process

Flowcharts of the C program

Below images show flowcharts for all featured software functions. Fist chart feature the main game function. Subfunctions are described below. See:

• draw
• reset_positons
• reset_screen

Main function Flowchart

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Subfunctions Flowcharts

This is the flowchart of the draw function. This function outputs the virtual screen to the matrix instruction register to be processed by VHDL.

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Flowchart of reset_position function. Function to reset positions of both paddles and ball to default. Default positions and values can be adjusted in this function

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Flowchart of reset_screen function. Function to reset all pixels of the virtual screen to 0.