DE2-115-FPGA-Pong/myfirst_niosii.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity myfirst_niosii is port (
		clk: in std_logic;
		rst: in std_logic;
		pio_led: out std_logic_vector(31 downto 0);
		buttons: in std_logic_vector(7 downto 0);
		matrix_rows: out std_logic_vector(11 downto 0);
		matrix_cols: out std_logic_vector(7 downto 0);
	   lcd_16207_ext_RS             : out   std_logic;                                        -- RS
	   lcd_16207_ext_RW             : out   std_logic;                                        -- RW
	   lcd_16207_ext_data           : inout std_logic_vector(7 downto 0)  := (others => 'X'); -- data
	   lcd_16207_ext_E              : out   std_logic 
);
type matrix_t is array(integer range 0 to 7) of std_logic_vector(11 downto 0);
end myfirst_niosii;

architecture behav of myfirst_niosii is
	component nios2_uc is port (
		clk_clk                 	  : in    std_logic                     := 'X';  				-- clk
		reset_reset_n           	  : in    std_logic                     := 'X';  				-- reset_n
		lcd_16207_ext_RS             : out   std_logic;                                        -- RS
		lcd_16207_ext_RW             : out   std_logic;                                        -- RW
		lcd_16207_ext_data           : inout std_logic_vector(7 downto 0)  := (others => 'X'); -- data
		lcd_16207_ext_E              : out   std_logic;                                        -- E
		pio_led_ext_conn_export 	  : out   std_logic_vector(31 downto 0);         				-- export
		pio_button_ext_conn_export   : in    std_logic_vector(7 downto 0)  := (others => 'X'); -- export
		pio_matrix_ext_conn_export   : out   std_logic_vector(19 downto 0)                     -- export
  
	);
	end component nios2_uc;

	signal button_states: std_logic_vector(7 downto 0);
	signal button_timer: integer range 0 to 2**20-1 := 0;

	signal matrix_timer: integer range 0 to 2**15-1 := 0;
	signal matrix_col_index: integer range 0 to 8 := 0;
	signal matrix_s: matrix_t;
	signal pio_matrix_s: std_logic_vector(19 downto 0);

begin
	 
	u0: component nios2_uc
	port map (
		clk_clk                 => clk, 
		pio_led_ext_conn_export => pio_led, 
		reset_reset_n           => rst,
		pio_matrix_ext_conn_export => pio_matrix_s,
		pio_button_ext_conn_export => button_states
	);



	matrix_set: process(clk, rst)
	variable col_id : integer range 0 to 8;
	begin
		if rst = '0' then
			matrix_s <= (
				"111110011111",
				"000100000101",
				"010000000111",
				"111110000000",
				"000000011111",
				"111110010001",
				"101010011111",
				"111010000000"
			);
		elsif rising_edge(clk) then
			col_id := to_integer(unsigned(pio_matrix_s(15 downto 12)));
			if col_id > 0 then
				matrix_s(col_id-1) <= pio_matrix_s(11 downto 0);
			end if;
		end if;
	end process;

	
	matrix_multiplex: process(clk, rst)

	begin
		if rst = '0' then
			matrix_rows <= "111111111111";
			matrix_cols <= "11111111";
			matrix_timer <= 0;
			matrix_col_index <= 0;
		elsif rising_edge(clk) then
			if matrix_timer = 2**15-1 then
				matrix_timer <= 0;
				if matrix_col_index = 7 then
					matrix_col_index <= 0;
				else
					matrix_col_index <= matrix_col_index + 1;
				end if;
				
				matrix_cols <= (others => '0');
				matrix_rows <= (others => '0');
			elsif matrix_timer = 2**11-1 then
				matrix_cols(matrix_col_index) <= '1';
				matrix_rows <= matrix_s(matrix_col_index);
				matrix_timer <= matrix_timer + 1;
			else
				matrix_timer <= matrix_timer + 1;
			end if;
		end if;
	end process;


	button_debounce: process(clk, rst)	
	begin
		if rst = '0' then
			button_timer <= 0;
		elsif rising_edge(clk) then
			if button_timer = 2**20-1 then
				button_timer <= 0;
				for id in 0 to 7 loop
					if buttons(id) = not button_states(id) then
						button_states(id) <= buttons(id);
						
					end if;
				end loop;
			else
				button_timer <= button_timer + 1;
			end if;
		end if;
	end process;
end behav;