queue size: 0 starting:nios2_uc "nios2_uc" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 5 modules, 21 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 5 modules, 20 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform 11 modules, 44 connections]]> Transform: IDPadTransform Transform: DomainTransform Transform merlin_domain_transform not run on matched interfaces nios2.data_master and nios2_data_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces nios2.instruction_master and nios2_instruction_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave Transform merlin_domain_transform not run on matched interfaces nios2_debug_mem_slave_translator.avalon_anti_slave_0 and nios2.debug_mem_slave Transform merlin_domain_transform not run on matched interfaces onchip_memory2_s1_translator.avalon_anti_slave_0 and onchip_memory2.s1 Transform merlin_domain_transform not run on matched interfaces pio_LED_s1_translator.avalon_anti_slave_0 and pio_LED.s1 22 modules, 114 connections]]> Transform: RouterTransform 28 modules, 138 connections]]> Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform 39 modules, 172 connections]]> Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform 41 modules, 212 connections]]> Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 6 modules, 22 connections]]> 6 modules, 22 connections]]> Transform: InterruptMapperTransform 7 modules, 26 connections]]> Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation 9 modules, 28 connections]]> nios2_uc" reuses altera_avalon_jtag_uart "submodules/nios2_uc_jtag_uart"]]> nios2_uc" reuses altera_nios2_gen2 "submodules/nios2_uc_nios2"]]> nios2_uc" reuses altera_avalon_onchip_memory2 "submodules/nios2_uc_onchip_memory2"]]> nios2_uc" reuses altera_avalon_pio "submodules/nios2_uc_pio_LED"]]> nios2_uc" reuses altera_mm_interconnect "submodules/nios2_uc_mm_interconnect_0"]]> nios2_uc" reuses altera_irq_mapper "submodules/nios2_uc_irq_mapper"]]> nios2_uc" reuses altera_reset_controller "submodules/altera_reset_controller"]]> queue size: 6 starting:altera_avalon_jtag_uart "submodules/nios2_uc_jtag_uart" Starting RTL generation for module 'nios2_uc_jtag_uart' Generation command is [exec /opt/intelFPGA/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios2_uc_jtag_uart --dir=/tmp/alt8585_5427978115204221252.dir/0002_jtag_uart_gen/ --quartus_dir=/opt/intelFPGA/18.1/quartus --verilog --config=/tmp/alt8585_5427978115204221252.dir/0002_jtag_uart_gen//nios2_uc_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios2_uc_jtag_uart' nios2_uc" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 5 starting:altera_nios2_gen2 "submodules/nios2_uc_nios2" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation nios2" reuses altera_nios2_gen2_unit "submodules/nios2_uc_nios2_cpu"]]> nios2_uc" instantiated altera_nios2_gen2 "nios2"]]> queue size: 38 starting:altera_nios2_gen2_unit "submodules/nios2_uc_nios2_cpu" Starting RTL generation for module 'nios2_uc_nios2_cpu' Generation command is [exec /opt/intelFPGA/18.1/quartus/linux64//eperlcmd -I /opt/intelFPGA/18.1/quartus/linux64//perl/lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=nios2_uc_nios2_cpu --dir=/tmp/alt8585_5427978115204221252.dir/0007_cpu_gen/ --quartus_bindir=/opt/intelFPGA/18.1/quartus/linux64/ --verilog --config=/tmp/alt8585_5427978115204221252.dir/0007_cpu_gen//nios2_uc_nios2_cpu_processor_configuration.pl --do_build_sim=0 ] # 2020.11.19 16:37:53 (*) Starting Nios II generation # 2020.11.19 16:37:53 (*) Checking for plaintext license. # 2020.11.19 16:37:53 (*) Couldn't query license setup in Quartus directory /opt/intelFPGA/18.1/quartus/linux64/ # 2020.11.19 16:37:53 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2020.11.19 16:37:53 (*) LM_LICENSE_FILE environment variable is empty # 2020.11.19 16:37:53 (*) Plaintext license not found. # 2020.11.19 16:37:53 (*) No license required to generate encrypted Nios II/e. # 2020.11.19 16:37:53 (*) Elaborating CPU configuration settings # 2020.11.19 16:37:54 (*) Creating all objects for CPU # 2020.11.19 16:37:54 (*) Generating RTL from CPU objects # 2020.11.19 16:37:54 (*) Creating plain-text RTL # 2020.11.19 16:37:55 (*) Done Nios II generation Done RTL generation for module 'nios2_uc_nios2_cpu' nios2" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 5 starting:altera_avalon_onchip_memory2 "submodules/nios2_uc_onchip_memory2" Starting RTL generation for module 'nios2_uc_onchip_memory2' Generation command is [exec /opt/intelFPGA/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios2_uc_onchip_memory2 --dir=/tmp/alt8585_5427978115204221252.dir/0003_onchip_memory2_gen/ --quartus_dir=/opt/intelFPGA/18.1/quartus --verilog --config=/tmp/alt8585_5427978115204221252.dir/0003_onchip_memory2_gen//nios2_uc_onchip_memory2_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios2_uc_onchip_memory2' nios2_uc" instantiated altera_avalon_onchip_memory2 "onchip_memory2"]]> queue size: 4 starting:altera_avalon_pio "submodules/nios2_uc_pio_LED" Starting RTL generation for module 'nios2_uc_pio_LED' Generation command is [exec /opt/intelFPGA/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios2_uc_pio_LED --dir=/tmp/alt8585_5427978115204221252.dir/0004_pio_LED_gen/ --quartus_dir=/opt/intelFPGA/18.1/quartus --verilog --config=/tmp/alt8585_5427978115204221252.dir/0004_pio_LED_gen//nios2_uc_pio_LED_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios2_uc_pio_LED' nios2_uc" instantiated altera_avalon_pio "pio_LED"]]> queue size: 3 starting:altera_mm_interconnect "submodules/nios2_uc_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 36 modules, 121 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.004s Timing: COM:3/0.025s/0.032s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.010s/0.011s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.004s Timing: COM:3/0.013s/0.017s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.010s/0.010s 40 modules, 133 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter"]]> nios2_uc" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 37 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_data_master_translator"]]> queue size: 35 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 31 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_data_master_agent"]]> queue size: 29 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 28 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 21 starting:altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 19 starting:altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> queue size: 15 starting:altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 13 starting:altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> queue size: 9 starting:altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 5 starting:altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> /home/sstudent/niosii_20201119/nios2_uc/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 3 starting:altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 40 starting:altera_irq_mapper "submodules/nios2_uc_irq_mapper" nios2_uc" instantiated altera_irq_mapper "irq_mapper"]]> queue size: 39 starting:altera_reset_controller "submodules/altera_reset_controller" nios2_uc" instantiated altera_reset_controller "rst_controller"]]> queue size: 6 starting:altera_avalon_jtag_uart "submodules/nios2_uc_jtag_uart" Starting RTL generation for module 'nios2_uc_jtag_uart' Generation command is [exec /opt/intelFPGA/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios2_uc_jtag_uart --dir=/tmp/alt8585_5427978115204221252.dir/0002_jtag_uart_gen/ --quartus_dir=/opt/intelFPGA/18.1/quartus --verilog --config=/tmp/alt8585_5427978115204221252.dir/0002_jtag_uart_gen//nios2_uc_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios2_uc_jtag_uart' nios2_uc" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 5 starting:altera_nios2_gen2 "submodules/nios2_uc_nios2" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation nios2" reuses altera_nios2_gen2_unit "submodules/nios2_uc_nios2_cpu"]]> nios2_uc" instantiated altera_nios2_gen2 "nios2"]]> queue size: 38 starting:altera_nios2_gen2_unit "submodules/nios2_uc_nios2_cpu" Starting RTL generation for module 'nios2_uc_nios2_cpu' Generation command is [exec /opt/intelFPGA/18.1/quartus/linux64//eperlcmd -I /opt/intelFPGA/18.1/quartus/linux64//perl/lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=nios2_uc_nios2_cpu --dir=/tmp/alt8585_5427978115204221252.dir/0007_cpu_gen/ --quartus_bindir=/opt/intelFPGA/18.1/quartus/linux64/ --verilog --config=/tmp/alt8585_5427978115204221252.dir/0007_cpu_gen//nios2_uc_nios2_cpu_processor_configuration.pl --do_build_sim=0 ] # 2020.11.19 16:37:53 (*) Starting Nios II generation # 2020.11.19 16:37:53 (*) Checking for plaintext license. # 2020.11.19 16:37:53 (*) Couldn't query license setup in Quartus directory /opt/intelFPGA/18.1/quartus/linux64/ # 2020.11.19 16:37:53 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2020.11.19 16:37:53 (*) LM_LICENSE_FILE environment variable is empty # 2020.11.19 16:37:53 (*) Plaintext license not found. # 2020.11.19 16:37:53 (*) No license required to generate encrypted Nios II/e. # 2020.11.19 16:37:53 (*) Elaborating CPU configuration settings # 2020.11.19 16:37:54 (*) Creating all objects for CPU # 2020.11.19 16:37:54 (*) Generating RTL from CPU objects # 2020.11.19 16:37:54 (*) Creating plain-text RTL # 2020.11.19 16:37:55 (*) Done Nios II generation Done RTL generation for module 'nios2_uc_nios2_cpu' nios2" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 5 starting:altera_avalon_onchip_memory2 "submodules/nios2_uc_onchip_memory2" Starting RTL generation for module 'nios2_uc_onchip_memory2' Generation command is [exec /opt/intelFPGA/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios2_uc_onchip_memory2 --dir=/tmp/alt8585_5427978115204221252.dir/0003_onchip_memory2_gen/ --quartus_dir=/opt/intelFPGA/18.1/quartus --verilog --config=/tmp/alt8585_5427978115204221252.dir/0003_onchip_memory2_gen//nios2_uc_onchip_memory2_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios2_uc_onchip_memory2' nios2_uc" instantiated altera_avalon_onchip_memory2 "onchip_memory2"]]> queue size: 4 starting:altera_avalon_pio "submodules/nios2_uc_pio_LED" Starting RTL generation for module 'nios2_uc_pio_LED' Generation command is [exec /opt/intelFPGA/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/intelFPGA/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios2_uc_pio_LED --dir=/tmp/alt8585_5427978115204221252.dir/0004_pio_LED_gen/ --quartus_dir=/opt/intelFPGA/18.1/quartus --verilog --config=/tmp/alt8585_5427978115204221252.dir/0004_pio_LED_gen//nios2_uc_pio_LED_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios2_uc_pio_LED' nios2_uc" instantiated altera_avalon_pio "pio_LED"]]> queue size: 3 starting:altera_mm_interconnect "submodules/nios2_uc_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 36 modules, 121 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 36 modules, 121 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.004s Timing: COM:3/0.025s/0.032s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.010s/0.011s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.004s Timing: COM:3/0.013s/0.017s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.010s/0.010s 40 modules, 133 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter"]]> nios2_uc" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 37 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_data_master_translator"]]> queue size: 35 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 31 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_data_master_agent"]]> queue size: 29 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 28 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 21 starting:altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 19 starting:altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> queue size: 15 starting:altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 13 starting:altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> queue size: 9 starting:altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 5 starting:altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> /home/sstudent/niosii_20201119/nios2_uc/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 3 starting:altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 40 starting:altera_irq_mapper "submodules/nios2_uc_irq_mapper" nios2_uc" instantiated altera_irq_mapper "irq_mapper"]]> queue size: 39 starting:altera_reset_controller "submodules/altera_reset_controller" nios2_uc" instantiated altera_reset_controller "rst_controller"]]> queue size: 38 starting:altera_nios2_gen2_unit "submodules/nios2_uc_nios2_cpu" Starting RTL generation for module 'nios2_uc_nios2_cpu' Generation command is [exec /opt/intelFPGA/18.1/quartus/linux64//eperlcmd -I /opt/intelFPGA/18.1/quartus/linux64//perl/lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /opt/intelFPGA/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=nios2_uc_nios2_cpu --dir=/tmp/alt8585_5427978115204221252.dir/0007_cpu_gen/ --quartus_bindir=/opt/intelFPGA/18.1/quartus/linux64/ --verilog --config=/tmp/alt8585_5427978115204221252.dir/0007_cpu_gen//nios2_uc_nios2_cpu_processor_configuration.pl --do_build_sim=0 ] # 2020.11.19 16:37:53 (*) Starting Nios II generation # 2020.11.19 16:37:53 (*) Checking for plaintext license. # 2020.11.19 16:37:53 (*) Couldn't query license setup in Quartus directory /opt/intelFPGA/18.1/quartus/linux64/ # 2020.11.19 16:37:53 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2020.11.19 16:37:53 (*) LM_LICENSE_FILE environment variable is empty # 2020.11.19 16:37:53 (*) Plaintext license not found. # 2020.11.19 16:37:53 (*) No license required to generate encrypted Nios II/e. # 2020.11.19 16:37:53 (*) Elaborating CPU configuration settings # 2020.11.19 16:37:54 (*) Creating all objects for CPU # 2020.11.19 16:37:54 (*) Generating RTL from CPU objects # 2020.11.19 16:37:54 (*) Creating plain-text RTL # 2020.11.19 16:37:55 (*) Done Nios II generation Done RTL generation for module 'nios2_uc_nios2_cpu' nios2" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 37 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_data_master_translator"]]> queue size: 35 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 31 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_data_master_agent"]]> queue size: 29 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 28 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 21 starting:altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 19 starting:altera_merlin_router "submodules/nios2_uc_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> queue size: 15 starting:altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 13 starting:altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> queue size: 9 starting:altera_merlin_demultiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 5 starting:altera_merlin_multiplexer "submodules/nios2_uc_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> /home/sstudent/niosii_20201119/nios2_uc/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 3 starting:altera_avalon_st_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 0 starting:error_adapter "submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]>