<?xml version="1.0" encoding="UTF-8"?>
<preferences>
 <debug showDebugMenu="0" />
 <systemtable filter="All Interfaces">
  <columns>
   <connections preferredWidth="143" />
   <irq preferredWidth="34" />
  </columns>
 </systemtable>
 <library
   expandedCategories="Library/Processors and Peripherals,Library/Processors and Peripherals/Peripherals,Library,Library/Interface Protocols,Library/Interface Protocols/PCI Express/QSYS Example Designs,Project,Library/Interface Protocols/PCI Express" />
 <window width="1440" height="860" x="0" y="-1" />
 <hdlexample language="VHDL" />
 <generation synthesis="VHDL" />
</preferences>
